Principal Application Engineer, VC Formal
Originally posted 20 September 2026 by the employer — open 1 day.
The Principal Application Engineer will apply VC Formal solutions.
About the role
This role involves leading the technical deployment of formal verification solutions and supporting customers in applying advanced verification techniques.
What you'll do
- Lead technical deployment of VC Formal solutions at customer sites, assessing verification environments and recommending formal methodologies.
- Analyze customer design blocks to identify targets for formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking.
- Diagnose root causes of tool performance issues, including state space explosion and convergence problems, then optimize formal test benches.
- Develop and deliver technical training to customer teams on new VC Formal features, product updates, and formal verification best practices.
- Work directly with Synopsys R&D and product engineering teams to communicate customer priorities and technical requirements.
- Support customers in applying formal verification to complex logic including data path verification, math functions, and sequential equivalence across design revisions.
What you'll need
- 10 to 15 years of hands-on experience in digital design verification with deep expertise in formal verification methodologies.
- Strong application knowledge of formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking.
- Proven experience diagnosing and resolving formal tool performance issues, including convergence problems and proof optimization.
- Solid understanding of RTL design, SystemVerilog, and verification test bench development.
- Experience working directly with customers in a technical consulting, application engineering, or field engineering role.
Skills: formal verification, VC Formal, property checking, sequential equivalence, test bench
This role has been open 0 days — well below the 60-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1136
|
Median days open
60 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1136 roles · 94 employers) |
|---|---|---|
| Open roles in this specialty | 62 | 1136 |
| Open roles in the wider Digital Design & Verification family | 131 | 3020 · 114 employers |
| Median days open | 16 d | 60 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: formal verification, VC Formal, property checking, sequential equivalence, test bench
Who's hiring in this category
- Qualcomm · 103 open roles · median 55 d
- AMD · 101 open roles · median 33 d
- NVIDIA · 89 open roles · median 67 d
- Synopsys (this employer) · 58 open roles · median 22 d
- Micron Technology · 56 open roles · median 100 d
- SiFive · 52 open roles · median 48 d
How we counted: 1136 open Design Verification (Design Verification) roles from 94 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.