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Synopsys

Principal Application Engineer- Emulation

Synopsys img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Austin, Texas, United States 19 days ago
Physical Design & EDA

Originally posted 16 September 2026 by the employer — open 2 days.

About the role

This role involves leading technical engagements with customers deploying emulation platforms and designing emulation strategies for complex SoC and ASIC projects.

What you'll do

  • Lead technical engagements with customers deploying ZeBu or other emulation platforms, diagnosing performance bottlenecks, debug issues, and workflow inefficiencies.
  • Design emulation strategies for complex SoC and ASIC projects, defining partitioning approaches, testbench integration, and bring-up sequences.
  • Collaborate directly with Synopsys R&D teams to escalate product gaps, influence roadmap priorities, and validate new features.
  • Develop and deliver technical training sessions, workshops, and best practice guides for customer engineering teams and internal application engineers.
  • Troubleshoot critical emulation failures in live customer environments, working across hardware, RTL, testbench, and software layers to isolate root cause.
  • Mentor junior applications engineers on emulation methodologies, debugging techniques, and customer engagement strategies.

What you'll need

  • 10+ years of hands-on experience with hardware emulation platforms such as Synopsys ZeBu, Mentor Veloce, or Cadence Palladium, including deployment, debug, and performance optimization.
  • Deep proficiency in hardware description languages including Verilog, SystemVerilog, and VHDL, with the ability to read, debug, and optimize RTL for emulation.
  • Strong understanding of verification methodologies including UVM, constrained random testing, and coverage-driven verification in the context of emulation environments.
  • Solid grasp of SoC and ASIC architecture, including subsystem integration, interconnect protocols, memory hierarchies, and software/hardware co-verification flows.
  • Experience with scripting languages such as Python, Perl, or TCL for automation, flow development, and data analysis in emulation and verification contexts.
  • Proven ability to debug complex interactions across RTL, testbenches, emulation hardware, and embedded software, isolating issues that span multiple domains.
  • Experience with customer-facing technical roles such as field applications engineering, customer support engineering, or technical consulting.

Skills: hardware emulation platforms, ZeBu, SystemVerilog, UVM, verification methodologies

Market context

This role has been open 0 days — well below the 86-day median for EDA/CAD Engineering roles.

EDA/CAD Engineering · EDA Tools

Open roles in category
680
Median days open
86 d
Median salary
$197k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Synopsys compares in EDA/CAD Engineering hiring
Metric Synopsys All employers we track in this specialty (680 roles · 73 employers)
Open roles in this specialty 55 680
Open roles in the wider Physical Implementation family 87 1379 · 105 employers
Median days open 57 d 86 d (−29 d vs this employer)
Median salary (USD postings) — $197k

Skills observed across this category: hardware emulation platforms, ZeBu, SystemVerilog, UVM, verification methodologies

Who's hiring in this category

  • Cadence Design Systems · 173 open roles · median 141 d
  • Synopsys (this employer) · 52 open roles · median 58 d
  • NVIDIA · 50 open roles · median 90 d
  • Micron Technology · 36 open roles · median 119 d
  • Qualcomm · 36 open roles · median 72 d
  • Intel Corporation · 29 open roles · median 23 d

How we counted: 680 open EDA/CAD Engineering (EDA Tools) roles from 73 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.

Synopsys

Synopsys

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img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Austin, Texas, United States
On-site
19 days ago

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