$165,000 - $210,000 USD yearly
Originally posted 25 September 2026 by the employer.
About the role
This role involves architecting and designing high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O. Your work will directly shape the performance, power, and reliability of products deployed in advanced data centers.
What you'll do
- Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, SerDes building blocks, ADCs/DACs, and clocking.
- Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.
- Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.
- Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering.
- Define and execute test plans to correlate silicon performance against design targets.
- Set analog design methodology, review standards, and best practices across the team.
What you'll need
- MS or PhD in Electrical Engineering or a related field.
- 8+ years of experience in analog and mixed-signal integrated circuit design.
- Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.
- Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.
- Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.
Nice to have
- Experience taking multiple analog/mixed-signal designs through full production tape-out and high-volume manufacturing.
- Expertise in high-speed serial link design (PCIe, Ethernet, UALink, UCIe) and associated PHY architectures.
- Familiarity with silicon debug, ATE test development, and design-for-test techniques.
- Experience mentoring engineers and leading technical design reviews.
Skills: Analog Mixed Signal Design Engineer, PLLs, LDOs, SerDes, PHY, high-speed I/O, ADCs/DACs, Cadence Virtuoso
This role has been open 31 days — well below the 104-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
150
|
Median days open
104 d
|
Median salary
$180k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (150 roles · 39 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 150 |
| Open roles in the wider Analog & Mixed-Signal family | 6 | 1461 · 106 employers |
| Median days open | 23 d | 104 d (−81 d vs this employer) |
| Median salary (USD postings) | — | $180k |
Skills observed across this category: Analog Mixed Signal Design Engineer, PLLs, LDOs, SerDes, PHY, high-speed I/O
Who's hiring in this category
- Analog Devices · 16 open roles · median 86 d
- SiTime · 11 open roles · median 216 d
- Infineon Technologies · 10 open roles · median 76 d
- Apple · 9 open roles · median 12 d
- Microchip Technology · 8 open roles · median 215 d
- NVIDIA · 8 open roles · median 41 d
How we counted: 150 open Mixed-Signal Design (Mixed Signal) roles from 39 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.