Principal Analog Mixed-Signal Design Engineer - San Jose, California, United States

Originally posted 11 September 2026 by the employer — open 0 days.

Design high-performance SerDes, PHY, and high-speed I/O for AI infrastructure.

About the role

This role involves architecting and designing high-performance analog and mixed-signal circuits that anchor SerDes, PHY, and high-speed I/O for rack-scale AI infrastructure. Your work directly shapes the performance, power, and reliability of products deployed in advanced data centers.

What you'll do

• Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.
• Drive circuit design from specification through schematic, layout supervision, and verification across PVT corners.
• Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.
• Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering.
• Define and execute test plans to correlate silicon performance against design targets.
• Set analog design methodology, review standards, and best practices across the team.

What you'll need

• MS or PhD in Electrical Engineering or a related field.
• 8+ years of experience in analog and mixed-signal integrated circuit design.
• Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.
• Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.
• Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.

Nice to have

• Experience taking multiple analog/mixed-signal designs through full production tape-out and high-volume manufacturing.
• Expertise in high-speed serial link design (PCIe, Ethernet, UALink, UCIe) and associated PHY architectures.
• Familiarity with silicon debug, ATE test development, and design-for-test techniques.
• Experience mentoring engineers and leading technical design reviews.

Skills: PLLs, LDOs, SerDes, ADCs/DACs, FinFET, Cadence Virtuoso