Principal Analog Mixed-Signal Design Engineer - Irvine, California, United States
$170,000 - $210,000 USD yearly
Originally posted 25 September 2026 by the employer.
About the role
This role involves architecting and designing high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O. This position specifically focuses on silicon building blocks that facilitate data movement for AI infrastructure, shaping performance, power, and reliability of products deployed in data centers.
What you'll do
- Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.
- Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.
- Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.
- Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering.
- Define and execute test plans to correlate silicon performance against design targets.
- Set analog design methodology, review standards, and best practices across the team.
What you'll need
- MS or PhD in Electrical Engineering or a related field.
- 8+ years of experience in analog and mixed-signal integrated circuit design.
- Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.
- Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.
- Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.
Nice to have
- Experience taking multiple analog/mixed-signal designs through full production tape-out and high-volume manufacturing.
- Expertise in high-speed serial link design (PCIe, Ethernet, UALink, UCIe) and associated PHY architectures.
- Familiarity with silicon debug, ATE test development, and design-for-test techniques.
- Experience mentoring engineers and leading technical design reviews.
Skills: SerDes, high-speed I/O, PLLs, FinFET, silicon bring-up
This role has been open 0 days — well below the 90-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
228
|
Median days open
90 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (228 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 228 |
| Open roles in the wider Analog & Mixed-Signal family | 7 | 1359 · 107 employers |
| Median days open | 125 d | 90 d (+35 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Skills observed across this category: SerDes, high-speed I/O, PLLs, FinFET, silicon bring-up
Who's hiring in this category
- AMD · 25 open roles · median 62 d
- Synopsys · 24 open roles · median 46 d
- Qualcomm · 20 open roles · median 62 d
- Cadence Design Systems · 19 open roles · median 168 d
- Micron Technology · 10 open roles · median 95 d
- NVIDIA · 10 open roles · median 139 d
How we counted: 228 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 25 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.