Principal Analog Mixed-Signal Design Engineer - Ho Chi Minh City, Vietnam
Originally posted 18 September 2026 by the employer.
About the role
This role involves designing high-speed analog and mixed-signal circuits for multi-gigabit transceivers. The position focuses on FinFET technology node.
What you'll do
- Design critical AMS blocks including PLLs, CDRs, TX drivers, RX front-ends, CTLEs, DFE, LDOs, bias generators, and ADC/DAC components for wireline transceivers.
- Perform transistor-level design, simulation, and optimization across process, voltage, and temperature (PVT) corners.
- Guide layout engineers on floorplanning, matching-sensitive layout, and parasitic-aware design.
- Perform design verification using pre- and post-layout simulations (transient, AC, noise, Monte Carlo, corner sweep).
- Create and maintain design documentation, design reviews, and specifications.
- Support silicon bring-up, lab measurement correlation, and debug of design issues.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.
- 8+ years of experience in analog/mixed-signal circuit design in deep-submicron or FinFET technologies.
- Strong experience with transistor-level design and simulation in advanced nodes (≤ 5nm).
- Experience designing analog blocks for high-speed transceivers.
- Strong experience with SPICE simulation tools and AMS verification environments.
- Deep understanding of noise, jitter, linearity, bandwidth, gain, impedance matching, and power trade-offs.
Skills: layout, advanced node CMOS, floor planning, DRC, LVS
This role has been open 12 days — well below the 82-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
692
|
Median days open
82 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (692 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 692 |
| Open roles in the wider Physical Implementation family | 24 | 1419 · 109 employers |
| Median days open | 93 d | 82 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: layout, advanced node CMOS, floor planning, DRC, LVS
Who's hiring in this category
- Cadence Design Systems · 169 open roles · median 161 d
- Synopsys · 53 open roles · median 47 d
- NVIDIA · 42 open roles · median 74 d
- Micron Technology · 41 open roles · median 109 d
- Qualcomm · 35 open roles · median 68 d
- GlobalFoundries · 27 open roles · median 49 d
How we counted: 692 open EDA/CAD Engineering (EDA Tools) roles from 76 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.