Principal AE, Serdes Design IP - San Jose, United States
$127,400 - $236,600 USD yearly
Originally posted 25 September 2026 by the employer.
Architect interface solutions for customers using Cadence Serdes IP.
About the role
As a Principal Applications Engineer, you will use your knowledge of different high-speed interface standards to architect interface solutions for customers using Cadence Serdes IP and showcase its performance.
What you'll do
- Technical presales and configuration of High-Speed Interface IP, including PCIe, CXL and Ethernet PHY and Controllers
- Present Cadence's IP portfolio and capabilities to prospective customers
- Serve as a product expert in digital controller and PHY IPs and protocols
- Provide quick-turn product specific technical support to customers, field teams, architects and designers
- Write application notes and articles for internal and/or external publication
- Demonstrate IP Performance at industry events and to prospective customers
What you'll need
- BS in EE, CE or related equivalent with 15+ years of relevant work experience or MS in EE, CE or equivalent with 10+ years of relevant work experience
- Solid experience in one or more high-speed interface protocols: PCIe, CXL, UCIe, Ethernet, USB, MIPI, 224G, 112G
- Strong knowledge of PHY and/or controllers for one or more high-speed interface protocols
- Individual leadership and initiative to manage pre-sales accounts
- Excellent presentation skills and verbal/written communication skills
Nice to have
- Lab validation and demo setup skills
- Experience on high-speed interface controller and/or PHY verification
- Knowledge of AXI and PIPE interface protocols
- Working knowledge of high-speed interface PHY
Skills: PCIe, CXL, Ethernet, Serdes IP, high-speed interface
This role has been open 19 days — well below the 57-day median for Applications FAE roles.
Applications FAE · Serdes Highspeed
|
Open roles in category
87
|
Median days open
57 d
|
Median salary
$183k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (87 roles · 23 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 87 |
| Median days open | 59 d | 57 d (+2 d vs this employer) |
| Median salary (USD postings) | — | $183k |
Skills observed across this category: PCIe, CXL, Ethernet, Serdes IP, high-speed interface
Who's hiring in this category
- Synopsys · 17 open roles · median 28 d
- Astera Labs · 16 open roles · median 60 d
- Keysight Technologies · 8 open roles · median 44 d
- Qualcomm · 8 open roles · median 66 d
- Microchip Technology · 6 open roles · median 42 d
- Marvell Technology · 5 open roles · median 172 d
How we counted: 87 open Applications FAE (Serdes Highspeed) roles from 23 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.