Principal 3D-heterogeneous integration engineer - United States
$85,000 - $146,000 USD yearly
Originally posted 11 September 2026 by the employer — open 9 days.
About the role
This role focuses on leading advanced 3D Heterogeneous Integration (3D-HI) initiatives, specifically driving process development for building blocks like multi-die stacking and fine pitch hybrid bonding.
What you'll do
- Drive 3D-HI process development for advanced packaging solutions.
- Partner with unit process engineers, manufacturing engineers, tool and material vendors.
- Collaborate on joint development projects for wafer level and die level 2.5D and 3D Heterogeneous Integration processes.
- Drive end-to-end process integration and planning for new capabilities and early product prototyping.
- Develop expertise in processes, materials, and tooling.
- Drive data analysis, interpretation of results, and understanding of failure modes.
What you'll need
- Master’s in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science, or a related field.
- 4-5 years of prior related work experience with an MS degree.
- In-depth knowledge of BEOL processes and integration (advanced bonding, TSVs), bump/wafer finish integration, wafer test/probe, OSAT collaboration, and package development & assembly.
- Strong problem solving and technical trouble shooting skills, including expertise in design of experiment.
- Minimum 3.0 GPA.
Nice to have
- PhD education level with 2-3 years of prior related work experience.
- Demonstrated prior leadership experience internally or with an OSAT eco-system.
- Project management skills.
Skills: 3D-HI process development, multi-die stacking, hybrid bonding, BEOL processes, wafer level and die level 2.5D and 3D Heterogeneous Integration
This role has been open 9 days — well below the 86-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
40
|
Median days open
86 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (40 roles · 21 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 40 |
| Median days open | 9 d | 86 d (−77 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Skills observed across this category: 3D-HI process development, multi-die stacking, hybrid bonding, BEOL processes, wafer level and die level 2.5D and 3D Heterogeneous Integration
Who's hiring in this category
- Qualcomm · 5 open roles · median 82 d
- Marvell Technology · 4 open roles · median 73 d
- Micron Technology · 4 open roles · median 129 d
- NVIDIA · 4 open roles · median 41 d
- AMD · 3 open roles · median 44 d
- Applied Materials · 2 open roles · median 70 d
How we counted: 40 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 21 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.