Pre-Silicon Verification Engineer - United States
$122,440 - $172,860 USD yearly
Originally posted 9 October 2026 by the employer.
This role focuses on functional accuracy and reliability of clock generator IPs like PLL and FLL.
About the role
This role involves ensuring the functional accuracy and reliability of clock generator IPs, such as PLL and FLL. You will be instrumental in the seamless integration of these IPs into Intel's designs.
What you'll do
- Develop test benches, verification environments, and tests using System Verilog and UVM.
- Perform functional verification for clock generator IPs such as PLL and FLL.
- Maintain and refine verification infrastructure and methodologies for multiple IP generations.
- Debug and root-cause pre-silicon issues within the verification environment.
- Document test plans and participate in technical reviews with design teams.
- Lead Mixed Signal Validation activities, including AMS simulations, schematic debugging, and resolving cross-functional issues.
What you'll need
- Bachelor's Degree in Electrical or Computer Engineering or a related field, with 4+ years of relevant experience; OR Master's Degree with 3+ years of relevant experience; OR PhD with 1+ year of relevant experience.
- 2+ years of experience in design verification and validation methodologies, including UVM, System Verilog, and industry-standard EDA tools.
- 2+ years of experience with scripting languages such as Python and Perl.
Nice to have
- Expertise in System Verilog UVM coding and debugging.
- Familiarity with PLL/FLL or SOC clocking and related RTL development.
Skills: UVM, System Verilog, test benches, PLL, FLL, AMS simulations
This role has been open 6 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 32 | 1195 |
| Open roles in the wider Digital Design & Verification family | 86 | 3204 · 115 employers |
| Median days open | 42 d | 64 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: UVM, System Verilog, test benches, PLL, FLL, AMS simulations
Who's hiring in this category
- Qualcomm · 109 open roles · median 37 d
- AMD · 97 open roles · median 51 d
- NVIDIA · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.