Pre-Silicon Validation Engineer
$101,400 - $152,200 USD yearly
Originally posted 1 October 2026 by the employer.
This role involves porting RTL designs onto industry-standard emulation platforms such as Cadence Palladium, Siemens Veloce, or FPGA prototyping systems.
About the role
This role involves supporting the development and validation of complex ASIC and FPGA-based designs with a focus on hardware emulation, RTL verification, system-level debugging, and software-hardware co-validation. You will work with industry-standard emulation platforms such as Cadence Palladium, Siemens Veloce, or FPGA prototyping systems.
What you'll do
- Develop, deploy, and maintain ASIC/FPGA emulation environments for complex SoC designs.
- Port RTL designs onto industry-standard emulation platforms such as Cadence Palladium, Siemens Veloce, or FPGA prototyping systems.
- Work closely with RTL, verification, architecture, and software teams to enable early hardware/software co-validation.
- Develop testbenches, transactors, and verification infrastructure using SystemVerilog and C/C++.
- Analyze and debug functional, performance, and system-level issues in emulation environments.
- Create automation scripts and workflows using Python to improve productivity, regression execution, and debug efficiency.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 0-2 years of experience in ASIC verification, FPGA prototyping, or hardware emulation.
- Expertise in SystemVerilog, C/C++, Linux environment, shell scripting, and Python programming.
- Experience with ASIC and FPGA Emulation platforms.
- Experience with RTL debugging, waveform analysis, and design verification methodologies.
- Knowledge of SoC architectures, bus protocols, and hardware/software interactions.
Nice to have
- Experience with Cadence Palladium, Protium, Siemens Veloce, or Synopsys ZeBu platforms.
- Familiarity with FPGA implementation flows using Xilinx or Intel FPGAs.
- Exposure to AI/ML technologies and AI-powered engineering tools.
- Knowledge of PCIe, CXL, DDR, Ethernet, or other high-speed interfaces.
- Experience with cloud-based compute environments and large-scale regression management.
Skills: ASIC/FPGA emulation, SystemVerilog, C/C++, RTL debugging, hardware/software co-validation
This role has been open 14 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 109 | 1192 |
| Open roles in the wider Digital Design & Verification family | 380 | 3183 · 115 employers |
| Median days open | 36 d | 65 d (−29 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: ASIC/FPGA emulation, SystemVerilog, C/C++, RTL debugging, hardware/software co-validation
Who's hiring in this category
- Qualcomm (this employer) · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.