Power Validation Engineer - San Jose, United States
Originally posted 30 April 2026 by the employer.
About the role
The Power Validation Engineer will own the end-to-end power characterization of the ASIC and mezzanine card platform from early silicon bring-up through production qualification. You will design measurement methodologies, build test benches, and drive findings directly into silicon, package, and system design decisions.
What you'll do
- Design and execute power measurement campaigns across all voltage rails (VDD_CORE, HBM, PCIe, AUX) under LLM inference and power virus workloads across PVT corners. - Validate power delivery network (PDN) performance—including VRM load step response, PCIe power compliance, and PDN impedance—to inform capacitor placement and de-cap strategy. - Profile power transient events (ramp rates, droop amplitudes, recovery profiles) and correlate them with on-die performance monitor data using automated sweep frameworks. - Validate power sequencing, PMBus telemetry accuracy, and BMC alert thresholds across cold-start, hot-restart, and fault-injection scenarios. - Run extended stress workloads (72 h+ continuous) to surface reliability risks and thermal throttling, supporting overseas partners with SLT, production, and debugging. - Feed characterization data back to RTL and physical design teams for DVFS policy, clock gating coverage, and leakage optimization.
What you'll need
- Bachelor’s degree in Electrical Engineering or a related field. - Deep understanding of ASIC and system-level power delivery, including VRM topology, PDN impedance, decoupling strategy, and transient response. - Hands-on bench experience with precision shunts, isolated differential probes, and VNA-based PDN impedance measurement. - Expertise with multi-phase solutions featuring high dynamic content and low tolerance. - Experience with VR tuning to power test plans to ensure specifications meet CPU/ASIC requirements. - Strong oscilloscope and lab instrument fluency for triggering on rare transient events and isolating root causes during silicon bring-up.
Nice to have
- Master’s degree in Power Electronics. - Experience with high voltage testing (800V and higher). - Prior power validation work on AI accelerators, GPUs, or server platforms, including HBM power characterization. - Experience with OpenBMC, IPMI, or custom BMC firmware for sensor monitoring and power capping, plus familiarity with LLM inference stacks (vLLM, TensorRT-LLM). - Proficiency in Python for test automation, data pipeline construction, and statistical analysis across PMBus register dumps and Linux kernel power management.
Skills: power measurement campaigns, voltage rails, LLM inference, power virus workloads, power delivery network (PDN) validation, silicon and firmware debug
This role has been open 177 days — well above the 114-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Silicon Validation
|
Open roles in category
185
|
Median days open
114 d
|
Median salary
$129k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (185 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 185 |
| Open roles in the wider Silicon Validation & Test family | 10 | 2238 · 112 employers |
| Median days open | 171 d | 114 d (+57 d vs this employer) |
| Median salary (USD postings) | — | $129k |
Skills observed across this category: power measurement campaigns, voltage rails, LLM inference, power virus workloads, power delivery network (PDN) validation, silicon and firmware debug
Who's hiring in this category
- Teradyne · 14 open roles · median 119 d
- Qualcomm · 12 open roles · median 114 d
- Renesas Electronics · 12 open roles · median 107 d
- Infineon Technologies · 9 open roles · median 122 d
- Marvell Technology · 9 open roles · median 122 d
- onsemi · 8 open roles · median 136 d
How we counted: 185 open Silicon Test Engineering (Silicon Validation) roles from 55 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.