Power Methodology and Modelling Engineer - CA, Santa Clara, United States

Originally posted 7 October 2026 by the employer.

About the role

This role focuses on driving SoC power efficiency methodology, primarily centered on RTL and architecture. The engineer will support the development of IP and SoC power models, analyze power-performance tradeoffs, and identify opportunities to improve power efficiency across AMD products.

What you'll do

• Contribute to SoC power methodology, RTL power analysis, and optimization to improve power efficiency across the SoC.
• Collaborate with architecture, RTL design, verification, and power teams to identify, evaluate, and implement power-efficiency features and enhancements.
• Analyze power and performance tradeoffs using power models, RTL simulations, workloads, and design data.
• Evaluate simulation and emulation traces for power projection and correlate projections with power-model predictions and silicon data.
• Support the development and continuous improvement of SoC power models and methodologies.
• Analyze power results, identify key power contributors and anomalies, and work with design teams to drive RTL power optimizations.
• Drive power-efficiency ideas from concept through RTL implementation, validation, and measurable power improvements.
• Apply power methodology and analysis techniques to identify and implement RTL and SoC-level power-efficiency enhancements.

What you'll need

• Strong foundation in RTL design, digital logic, and SoC architecture.
• Experience with, or strong interest in, RTL power analysis, low-power design techniques, power methodology, and power-efficiency optimization.
• Understanding of power-management concepts and how architecture and RTL design decisions impact SoC power and performance.
• Exposure to power modeling, power projection, and model-based power analysis methodologies.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Nice to have

• Exposure to CPU, memory subsystems, fabrics, I/O, clocking, or power-management features.
• Experience with hardware emulation and the use of emulation traces for power projection and analysis.
• Interest in learning and growing expertise in SoC power modeling, methodology development, power projection, validation, and correlation.
• Programming and scripting experience, with Python preferred.
• Strong analytical and problem-solving skills with the ability to identify and drive power-efficiency opportunities across engineering disciplines.

Skills: SoC power efficiency, RTL power analysis, low-power design, power modeling, power-management concepts