Power Management Design Engineer - United States
$139,752 - $170,808 USD yearly
Originally posted 8 August 2026 by the employer.
Design, architect, and implement power management, reset, and clocking solutions for RISC-V CPU and SoC IP.
About the role
This role involves creating power management, reset, and clocking solutions for RISC-V CPU and SoC IP designs.
What you'll do
- Work with the architecture team to understand and define power management requirements.
- Architect, design, and implement core clocking, reset, and power management solutions.
- Develop and specify microarchitecture, ensuring knowledge sharing through documentation.
- Perform initial sandbox verification and collaborate with the design verification team on test plans.
- Work with the physical implementation team to optimize physical design for frequency, area, and power goals.
- Collaborate with the software team to enable and optimize power management features.
What you'll need
- 3+ years of recent industry experience in CPU and SoC clocking, reset, and power-management logic designs.
- Experience in high-performance, energy-efficient CPU and SoC designs.
- Expertise in CPU and SoC clocking, reset design, and power management, including: reset control and design strategies, clock distribution, dynamic clocking, clock gating, clock boundary crossing strategies, power state definition and management, Power Management Unit (PMU) design, dynamic and static power reduction techniques (including retention and power-up/down sequencing), Dynamic Voltage and Frequency Scaling (DVFS), and Di/dt mitigation strategies.
- Understanding of DFT, MBIST, Debug, and Error handling in CPU designs.
- Experience with power-aware simulation.
- Proficiency with hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
- Understanding of RTL quality checks like Lint, CDC, RDC.
- Background of successful CPU or SoC development from architecture through tapeout.
Nice to have
- Experience with AMBA Interconnect Protocols, such as AXI, AHB, and APB.
- Experience with AMBA Low Power Protocol Interface, including P-channel and Q-channel protocols.
- Experience with Scala/Chisel, Bluespec, or other languages/DSLs for expressing configurable hardware.
- Knowledge of RISC-V architecture.
- Experience with Git/Github, Jira, Confluence.
Skills: power management, reset design, clocking solutions, RTL design, RISC-V
This role has been open 75 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1070
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiFive | All employers we track in this specialty (1070 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 1070 |
| Open roles in the wider Digital Design & Verification family | 86 | 3299 · 116 employers |
| Median days open | 78 d | 62 d (+16 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: power management, reset design, clocking solutions, RTL design, RISC-V
Who's hiring in this category
- Qualcomm · 153 open roles · median 58 d
- Synopsys · 87 open roles · median 35 d
- AMD · 76 open roles · median 40 d
- Analog Devices · 49 open roles · median 51 d
- NXP Semiconductors · 42 open roles · median 90 d
- NVIDIA · 41 open roles · median 62 d
How we counted: 1070 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.