Power Management Architect - Santa Clara, CA, United States
$125,000 - $500,000 USD yearly
Originally posted 27 July 2026 by the employer.
Architect power delivery, distribution, and management for Physical AI System-on-Chip (SoC).
About the role
As Power Management Architect for Velaura AI, you will own the power architecture of the Physical AI System-on-Chip (SoC), defining how the chip delivers, distributes, and manages energy across compute, AI/NPU, memory, and I/O.
What you'll do
- Own the SoC power architecture: define power domains, voltage/frequency (DVFS) strategy, power states, and the power delivery network.
- Define dynamic and static power management techniques including clock and power gating, adaptive voltage scaling, body biasing, and retention strategies.
- Establish power and energy budgets and model them across use cases; drive power, performance, and area (PPA) trade-offs.
- Architect the on-die power management and control subsystem, including PMIC interface, power management controller, sensors, and telemetry.
- Partner with silicon design, firmware, thermal, package, and platform software teams to embed power intent (e.g., UPF) into the design flow.
- Define power and thermal management for sustained real-world operation, including thermal throttling and energy-aware scheduling.
What you'll need
- 8+ years in power management, mixed-signal, or SoC architecture, with experience defining power architecture for shipping silicon or embedded platforms.
- Deep expertise in low-power design techniques: multiple power domains, DVFS, clock/power gating, adaptive voltage scaling, retention, and power state management.
- Strong understanding of power delivery networks, PMICs, voltage regulation, and the interaction between power, thermal, and package constraints.
- Hands-on experience with power intent and low-power methodology (e.g., UPF/CPF) and with power modeling and analysis.
- Experience working across silicon design, firmware, and platform software to define and validate power management policies.
- Bachelor’s or advanced degree in Electrical/Computer Engineering or a related field, or equivalent practical experience.
Nice to have
- Experience optimizing power for AI/ML accelerators or NPUs and for real-time or latency-sensitive edge workloads.
- Familiarity with robotics, automotive, mobile, or other power- and thermally-constrained domains, and with battery and energy-storage considerations.
- Experience with energy-aware software/firmware, thermal management, and silicon power characterization and correlation.
- Prior experience at an early-stage or high-growth semiconductor or hardware company, building power architecture and methodology from the ground up.
Skills: SoC power architecture, power domains, DVFS, power delivery network, PMIC, low-power design techniques
This role has been open 82 days — slightly above the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
472
|
Median days open
79 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Velaura AI | All employers we track in this specialty (472 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 472 |
| Open roles in the wider Digital Design & Verification family | 26 | 3201 · 115 employers |
| Median days open | 83 d | 79 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: SoC power architecture, power domains, DVFS, power delivery network, PMIC, low-power design techniques
Who's hiring in this category
- Qualcomm · 73 open roles · median 88 d
- NVIDIA · 56 open roles · median 71 d
- Apple · 36 open roles · median 12 d
- AMD · 34 open roles · median 60 d
- Arm Holdings · 27 open roles · median 115 d
- Micron Technology · 22 open roles · median 107 d
How we counted: 472 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.