Power Integrity Engineer-Silicon - San Jose, United States

Originally posted 17 June 2026 by the employer.

Lumilens is developing high-speed photonics products to power the future of AI infrastructure and high-performance computing.

About the role

This role involves defining and implementing power delivery strategies across complex 2.5D/3D packages that integrate electrical ICs, photonic ICs, chiplets, and high-bandwidth memory. You will architect robust, low-noise, high-efficiency PDNs for AI clusters without compromising performance or reliability.

What you'll do

• Define and implement power integrity architectures for 2.5D/3D heterogeneous integration, including chiplet-based designs, interposer/substrate scaling, on-package voltage regulation, multi-rail PDN topologies, decoupling strategies, and power-aware thermal co-design.
• Perform full-stack power integrity analysis and optimization from die-level IR drop to package-level PDN impedance profiling, transient response, and system-level PDN validation.
• Model, simulate, and validate power delivery solutions using Ansys SIwave, HFSS, Cadence Sigrity, Apache RedHawk, Voltus, or equivalent tools across silicon, interposer, substrate, and board interfaces.
• Lead power integrity co-design with silicon design, package engineering, and photonics teams to optimize bump maps, power/ground grid layouts, TSV/RDL routing, on-die decoupling, and voltage regulator placement for minimal noise, IR drop, and EMI in CPO/NPO systems.
• Drive selection and qualification of advanced power components and collaborate with foundry/OSAT partners on PDN process capabilities, manufacturability, yield, and cost.
• Analyze and mitigate power-related reliability risks, including electromigration, thermal-induced voltage droop, power sequencing, and long-term stability under dynamic AI workloads.

What you'll need

• Deep expertise in power integrity for high-performance semiconductors, with knowledge of PDN design principles, frequency-domain analysis, transient response, on-chip/off-chip decoupling, IR drop/EM analysis, and noise mitigation techniques.
• Proven track record leading power integrity efforts in advanced packaging environments, including 2.5D/3D integration, chiplets, silicon interposers/bridges, FOWLP, CoWoS, hybrid bonding, or similar technologies.
• Bachelor’s degree in Electrical Engineering, Physics, or related field + 10+ years relevant industry experience; or Master’s/PhD + 7+ years related experience.
• Hands-on proficiency with PI simulation tools (Ansys, Cadence/Sigrity, Keysight ADS, Apache/RedHawk, or equivalents) and correlation to silicon measurements.
• Strong understanding of chip-package-system interactions, high-speed signaling impacts on PDN, power-aware design for AI/HPC workloads, photonic interconnects and optical engines, and reliability failure mechanisms (e.g., EM, TDDB under high current densities).
• Demonstrated ability to lead complex, cross-functional programs across global teams, foundries, OSATs, and suppliers.

Nice to have

• Experience with power integrity in silicon photonics, CPO/NPO, photonic IC/laser integration, or high-bandwidth optical interconnects for AI accelerators.
• Prior work defining long-term PDN roadmaps and executing from concept through high-volume manufacturing in hyperscale AI or HPC environments.
• Leadership in multi-supplier or multi-company power integrity initiatives with measurable impact on performance, efficiency, or cost.
• Familiarity with signal integrity/power integrity co-optimization, high-speed SerDes, PCIe/CXL interfaces, HBM integration, or advanced memory subsystems.
• Familiarity with photonic and electrical IC foundry processes (BICMOS, Advanced node CMOS).
• Knowledge of board/system-level power delivery requirements and multi-physics considerations (thermal-electrical coupling).

Skills: power integrity, 2.5D/3D packaging, chiplets, PDN, photonic interconnects, AI accelerators