Power Integrity Engineer - San Jose, United States

Originally posted 30 July 2026 by the employer.

Join our platform electrical engineering team to own the power integrity methodology for high-power PCB and system designs.

About the role

As a Power Integrity (PI) Engineer, you will own the power integrity methodology for high-power PCB and system designs, from early architecture through final release, ensuring robust power delivery to high-performance ASICs and supporting components across all operating conditions.

What you'll do

• Perform pre- and post-layout PDN analysis for high-current ASIC power rails, including target impedance profiling, decoupling capacitor selection, and plane resonance analysis.
• Execute DC IR-drop and current density simulations; define copper weight, plane shapes, via stitching, and layer allocation requirements for PCB designers.
• Conduct AC impedance analysis from VRM output through package and die, including ESR/ESL modeling of the full decoupling network.
• Develop and validate VRM models; analyze load transient response, AVP/load-line behavior, and multiphase converter performance against ASIC power specifications.
• Perform power-plane thermal co-simulation and collaborate on thermal-electrical tradeoffs for high-current delivery.
• Drive design rule checks for PI compliance; work with layout teams using Cadence Allegro / Sigrity PowerDC/PowerSI or Ansys SIwave.

What you'll need

• B.S. or M.S. in Electrical Engineering or a closely related discipline.
• 5+ years of hands-on PI experience on high-current, high-performance designs (ASIC/CPU/GPU power delivery, server boards, or accelerator platforms).
• Proficiency with industry PI EDA tools (Ansys SIwave, Cadence Sigrity PowerDC/PowerSI/OptimizePI, or equivalent).
• Strong understanding of target impedance methodology, decoupling network design, plane resonances, and anti-resonance mitigation.
• Experience with DC IR-drop analysis, current density limits, and via/plane current-carrying capacity.
• Working knowledge of VRM fundamentals: buck converter operation, multiphase design, transient response, and load-line/AVP concepts.
• Working knowledge of multi-layer PCB stack-up design and power plane allocation strategies.

Nice to have

• Prior work in data center, AI/ML accelerator, networking, or high-performance computing (HPC) hardware environments.
• Experience with vertical power delivery, high-current lateral delivery tradeoffs, or 48V-to-point-of-load architectures.
• Package-level PDN co-analysis and experience working with die/package power models from ASIC teams.
• Experience scripting automated PI simulation flows using Python or MATLAB to reduce manual simulation turnaround time.

Skills: PDN analysis, IR-drop, VRM models, thermal co-simulation, Cadence Allegro