Power Integrity Engineer - Mountain View, CA, United States
$157,000 - $176,000 USD yearly
Originally posted 19 August 2026 by the employer — open 21 days.
About the role
What you'll do
- Support design and analysis of Power Delivery Networks (PDNs) for digital and analog SoC domains.
- Assist in modeling regulator characteristics to aid in component selection.
- Use commercial simulation tools (e.g., 2.5D EM solvers) to extract PCB and package impedance profiles and generate N-port models.
- Perform time-domain and frequency-domain simulations to evaluate supply rail behavior.
- Conduct lab measurements using programmable loads and oscilloscopes to validate power integrity design.
- Work closely with hardware designers, layout engineers, and system integrators to implement PDN design improvements.
What you'll need
- M.S. or Ph.D. in Electrical Engineering or a related field.
- 3+ years of experience in power delivery and power integrity analysis for high performance CPUs and compute SoCs.
- Proficiency in using simulation and analysis tools for power integrity, including PowerSI, PowerDC, IDEM, H-Spice and Keysight ADS.
- Experience in DC-DC converter design.
- Experience with PCB design and layout considerations for power integrity, including layer stack-up assignment, power plane partitioning, capacitor selection and placement, and microvia/PTH design.
- Strong problem-solving and debugging skills for power integrity-related issues.
Nice to have
- Working knowledge of different 2D/2.5D/3D packaging technologies and associated PDN challenges.
- Familiarity in using lab equipment for signal measurement and characterization, such as oscilloscopes and network analyzers.
- Proficiency in scripting languages such as Skill, TCL, Python, and Matlab for automation of design and modeling flows and post-processing results.
Skills: Power Integrity, PDN, DC-DC converter, PowerSI, oscilloscopes, PCB design
This role has been open 21 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lightmatter | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 6 | 1317 · 100 employers |
| Median days open | 100 d | 91 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Power Integrity, PDN, DC-DC converter, PowerSI, oscilloscopes, PCB design
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.