Power IC Design Engineer - Shanghai, Pudong, ZuChongzhi, China
Originally posted 2 July 2026 by the employer — open 81 days.
About the role
As a Staff Power IC Design Engineer, you will develop high-performance power management circuit blocks within integrated circuits at ADI's Shanghai design center. This role involves executing complex power designs from schematic through silicon validation.
What you'll do
- Design and implement power management circuit blocks at the transistor level, including DC-DC converters, LDOs, charge pumps, gate drivers, power stages, and protection circuits.
- Execute designs from schematic capture through simulation, layout oversight, and post-layout verification.
- Perform parasitic-aware simulation, power-stage optimization, and design centering across process corners and operating conditions.
- Optimize transient response, loop bandwidth, and load regulation through iterative simulation and bench correlation.
- Support silicon bring-up, debug, and correlation of measured results against simulation predictions.
- Collaborate with design teams on architecture trade-offs across efficiency, area, EMI, reliability, and cost.
What you'll need
- MSEE with 7+ years of power IC design experience, or PhD with 5+ years.
- Strong transistor-level design skills for high-performance power management circuits.
- Demonstrated ability to deliver power IC designs through tape-out, silicon validation, and production release.
- Solid understanding of BCD, HV-CMOS, and power FET process technologies, including high-voltage device physics and safe operating area constraints.
- Proficiency with Cadence IC design suite: Virtuoso, Spectre/APS, and power-stage simulation environments.
- Experience with control loop design, compensation techniques, and stability analysis for switching and linear regulators.
- Fluent in Mandarin and strong English written and verbal communication skills.
Nice to have
- Experience with magnetics modeling, inductor/transformer co-design, and system-level power delivery network analysis.
- Knowledge of thermal analysis, package-level power dissipation modeling, and EMI/EMC mitigation techniques.
- Curiosity and initiative to explore AI/ML techniques and emerging tools.
Skills: power management circuit blocks, DC-DC converters, LDOs, charge pumps, silicon validation, Cadence Virtuoso
This role has been open 88 days — well above the 72-day median for Power Electronics roles.
Power Electronics · Power Management
|
Open roles in category
71
|
Median days open
72 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Analog Devices | All employers we track in this specialty (71 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 71 |
| Open roles in the wider Analog & Mixed-Signal family | 82 | 1337 · 105 employers |
| Median days open | 82 d | 72 d (+10 d vs this employer) |
| Median salary (USD postings) | — | $169k |
Skills observed across this category: power management circuit blocks, DC-DC converters, LDOs, charge pumps, silicon validation, Cadence Virtuoso
Who's hiring in this category
- Renesas Electronics · 15 open roles · median 76 d
- Qualcomm · 8 open roles · median 39 d
- Analog Devices (this employer) · 6 open roles · median 82 d
- Monolithic Power Systems · 6 open roles · median 185 d
- AMD · 5 open roles · median 90 d
- Infineon Technologies · 5 open roles · median 73 d
How we counted: 71 open Power Electronics (Power Management) roles from 25 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.