Post-Silicon Validation, Sr Staff Engineer
Originally posted 5 October 2026 by the employer.
This role focuses on UCIe validation for die-to-die interface IP.
About the role
This role involves owning post-silicon electrical validation and characterization strategy for UCIe die-to-die interface IP, from test plan definition through silicon sign-off.
What you'll do
- Own post-silicon electrical validation and characterization strategy for UCIe die-to-die interface IP
- Architect and develop software solutions for lab automation, result processing, and silicon debug using Python, C, and C++
- Lead complex debug efforts spanning circuit design, package, interposer, link training firmware, and protocol layer interactions
- Support customers directly with silicon bring-up and debug, including sideband and mainband link training
- Develop characterization methodology for die-to-die links using on-die instrumentation, eye margining, and bench equipment like oscilloscopes, BERTs, and spectrum analyzers
- Review and approve the work of other validation engineers, providing technical mentorship
What you'll need
- Bachelor's degree in Electrical Engineering or Computer Engineering with 8+ years, or Master's with 6+ years of related experience
- Extensive hands-on experience in post-silicon validation, characterization, and debug of high-speed mixed-signal interface IP
- Working knowledge of the UCIe specification, including PHY, D2D adapter layers, link initialization, and sideband operation
- Advanced software development capability across Python, C, and C++, with strong command of software engineering best practices, data structures, and algorithms
- Demonstrated experience architecting complex software projects, including lab automation frameworks and Python UI development
- Expert-level debug experience with high-speed oscilloscopes, BERTs, spectrum analyzers, and network analyzers
- Experience supporting customer silicon bring-up and debug, including working in a customer lab environment and communicating findings
Nice to have
- Direct experience with UCIe or another die-to-die interface
- High-speed SerDes experience
- Experience with software version control systems such as GitLab, Jira, and Confluence
- Experience with Signals & Systems concepts, transmission line theory, and high-speed link analysis applied to package, interposer, and substrate channels
This role has been open 9 days — well below the 64-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
118
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (118 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 118 |
| Open roles in the wider Silicon Validation & Test family | 17 | 2220 · 112 employers |
| Median days open | 9 d | 64 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 37 d
- AMD · 15 open roles · median 63 d
- NVIDIA · 15 open roles · median 70 d
- Graphcore · 10 open roles · median 121 d
- Amazon · 6 open roles · median 40 d
- Micron Technology · 5 open roles · median 211 d
How we counted: 118 open Post-Silicon Validation (Design Verification) roles from 30 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.