Post-Silicon Validation, Senior Manager
Originally posted 5 October 2026 by the employer.
Own the silicon data behind UCIe IP releases and the customer relationships that depend on it being right.
About the role
This role involves leading a post-silicon validation team responsible for characterization and validation of internal silicon testchips and supporting customer silicon bring up for UCIe die-to-die interface IP.
What you'll do
- Lead and manage a team of validation and characterization engineers supporting UCIe-based die-to-die interface IP.
- Own the characterization and validation of internal silicon testchips end to end, from characterization plan definition through silicon sign-off.
- Own the customer silicon bring up and debug mission, including sideband and mainband link training, lane repair, and chiplet interoperability.
- Oversee operational and functional objectives for the group and allocate personnel resources to meet schedules and goals.
- Establish standards and methodologies governing characterization execution, measurement practice, silicon sign-off criteria, and customer lab engagement.
- Own the escalation path for critical silicon issues, ensuring technical depth is applied and program/customer risk is communicated.
What you'll need
- Bachelor's degree in Electrical or Computer Engineering with a minimum of 10 years of related experience, or an advanced degree with a minimum of 8 years of related experience.
- Demonstrated people management experience in a silicon or hardware engineering organization.
- Extensive hands-on background in post-silicon characterization, validation, and debug of high-speed mixed-signal interface IP.
- Working knowledge of the UCIe specification and die-to-die ecosystem, including PHY and D2D adapter layers, link training, and packaging tradeoffs.
- Experience owning R&D lab operations, including capital equipment planning and high-speed instrumentation such as oscilloscopes, BERTs, spectrum analyzers, and network analyzers.
- Familiarity with validation software and automation development practice across Python, C, and C++.
- Proven track record engaging major customers on technical matters, including silicon bring up support and issue escalation.
This role has been open 9 days — well below the 64-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
118
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (118 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 118 |
| Open roles in the wider Silicon Validation & Test family | 17 | 2220 · 112 employers |
| Median days open | 9 d | 64 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 37 d
- AMD · 15 open roles · median 63 d
- NVIDIA · 15 open roles · median 70 d
- Graphcore · 10 open roles · median 121 d
- Amazon · 6 open roles · median 40 d
- Micron Technology · 5 open roles · median 211 d
How we counted: 118 open Post-Silicon Validation (Design Verification) roles from 30 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.