Post-Silicon Validation, Principal Engineer
Originally posted 5 October 2026 by the employer.
Define the post-silicon validation and characterization strategy for UCIe-based die-to-die interface IP.
About the role
This role involves defining the post-silicon validation and characterization strategy for die-to-die interface IP, acting as the final technical escalation point for silicon issues. The role focuses on UCIe die-to-die IP validation and silicon sign-off decisions.
What you'll do
- Define post-silicon validation and characterization strategy for UCIe-based die-to-die interface IP.
- Act as the final technical escalation point for silicon issues across analog circuit behavior, package effects, link training firmware, protocol layer, and system integration.
- Lead bring up and debug of customer silicon, resolving link training failures, lane repair issues, and chiplet interoperability problems.
- Own the architecture and technical direction of the validation software platform in Python, including lab automation frameworks and data infrastructure.
- Establish characterization methods for die-to-die links with limited probe access, using on-die instrumentation, eye margining, and built-in monitors.
- Drive validation programs across analog design, digital design, firmware, product engineering, applications, and marketing.
What you'll need
- Bachelor's degree in Electrical Engineering or Computer Engineering with 10+ years of related experience, or advanced degree with 8+ years of related experience.
- Extensive expertise in post-silicon validation, characterization, and debug of high-speed mixed-signal interface IP across multiple silicon generations and process nodes.
- Authoritative command of the UCIe specification, including PHY, D2D adapter layers, link initialization and training, sideband operation, lane repair and reversal.
- Recognized depth in high-speed link analysis, including equalization, jitter decomposition, crosstalk, and package, interposer, and substrate channel behavior.
- Advanced software architecture capability across multiple languages including Python, with experience building large-scale lab automation frameworks, data infrastructure, and measurement correlation systems.
- Expert-level command of high-speed oscilloscopes, BERTs, spectrum analyzers, and network analyzers.
Nice to have
- Direct UCIe or other die-to-die interface experience.
- Deep high-speed SerDes experience.
- Experience with software version control systems such as GitLab.
- Experience with issue and task tracking through Jira and Confluence.
This role has been open 9 days — well below the 64-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
118
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (118 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 118 |
| Open roles in the wider Silicon Validation & Test family | 17 | 2220 · 112 employers |
| Median days open | 9 d | 64 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 37 d
- AMD · 15 open roles · median 63 d
- NVIDIA · 15 open roles · median 70 d
- Graphcore · 10 open roles · median 121 d
- Amazon · 6 open roles · median 40 d
- Micron Technology · 5 open roles · median 211 d
How we counted: 118 open Post-Silicon Validation (Design Verification) roles from 30 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.