Post Silicon High-Speed I/O Validation Engineer - TX, Austin, United States
Originally posted 2 October 2026 by the employer.
This role focuses on high-speed I/O technologies like UCIe, UALink, PCI Express, and CXL.
About the role
This role involves developing and executing feature enablement and validation test plans for SoC- and system-level SoC features across AMD Server products, focusing on High-Speed IO, including inter-die interface UCIe, UALink, PCI Express, CXL, and multi-socket interfaces.
What you'll do
- Develop and execute feature enablement and validation test plans for SoC- and system-level SoC features across all AMD Server products for High-Speed IO
- Develop test content for both focus testing as well as system level stress testing of IO domain plus cross product stress testing
- Develop post-silicon validation infrastructure (software, hardware, automation environment, and lab setup)
- Debug and drive root-cause analysis for SoC related issues
- Collaborate with cross-functional teams in developing tools to improve SoC validation and debug
- Work with cross-functional teams to improve post-silicon validation test strategy, methodology, and process
What you'll need
- Bachelor's or Master's Degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent
- Experience developing validation methodologies and infrastructure
- Test plan and workload development experience
- Debug skills at both SoC and system level
- Familiarity with programming / scripting language (C/C++, Python, Perl, ...)
- Working knowledge of Server OSes (Linux, Windows)
Nice to have
- Leadership experience in soc design or validation
- Experience in UCIe, UALink, PCIe Gen5/6+, CXL, UCIe or proprietary inter-die and multi-socket server interface in either electrical or functional or both
- Understanding of modern x86 microprocessor architecture and Server platform architecture
- Participated in silicon bring up and debug, support to internal engineering teams
- Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
- Extensive experience with board/platform-level debug, including delivery, sequencing, analysis, and optimization
- Extensive knowledge of system architecture, technical debug, and validation strategy
This role has been open 7 days — well below the 53-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
123
|
Median days open
53 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (123 roles · 28 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 123 |
| Open roles in the wider Silicon Validation & Test family | 159 | 2209 · 111 employers |
| Median days open | 58 d | 53 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 20 open roles · median 31 d
- AMD (this employer) · 18 open roles · median 46 d
- NVIDIA · 16 open roles · median 63 d
- Graphcore · 11 open roles · median 114 d
- Amazon · 6 open roles · median 33 d
- Synopsys · 6 open roles · median 2 d
How we counted: 123 open Post-Silicon Validation (Design Verification) roles from 28 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.