Platform Validation Lead - IO Interfaces - TX, Austin, United States
Originally posted 1 October 2026 by the employer.
About the role
This role involves leading system validation and debug for datacenter CPU and AI post-silicon validation, focusing on highspeed IO interfaces such as PCI Express, CXL, or RAS, within AI GPU systems.
What you'll do
- Develop and execute feature enablement and validation test plans for SoC- and system-level features across AMD Server and AI products.
- Leverage AI/ML technologies to enhance post-silicon validation, debug, and test automation efficiency, including data analytics and failure triage.
- Develop test content for focus testing and system-level stress testing of IO domain and cross-product stress testing.
- Develop post-silicon validation infrastructure (software, hardware, automation environment, and lab setup).
- Collaborate with partner organizations to provide root cause analysis for platform issues in a Data center environment, including SoC logical, performance, and BIOS/firmware issues.
What you'll need
- 8+ years of experience with a BSEE/CSE/CS or 6+ years of experience with an MSEE/CSE/CS.
- Domain expertise in IO interfaces such as PCIe, CXL, or RAS for comprehensive system level test-plan execution.
- Strong understanding of Server platform components and x86 or other complex CPU architectures.
- Experience developing validation test-plans, execution, and debug skills at SoC/Platform level.
- Experience with board/platform-level debug, including delivery, sequencing, analysis, and optimization.
- Experience with Oscilloscopes, protocol analyzers, and JTAG based Debug Tools.
Nice to have
- Proficiency with Linux and/or Microsoft Operating Systems.
- Familiarity with programming / scripting language (C/C++, Python, Perl, ...).
- Knowledge of pre-silicon environments (Verification, Emulation, Virtual Bring-Up).
Skills: post silicon validation, highspeed IO, PCI Express, CXL, AI GPU systems
This role has been open 8 days — well below the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
401
|
Median days open
41 d
|
Median salary
$174k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (401 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 57 | 401 |
| Open roles in the wider Silicon Validation & Test family | 159 | 2209 · 111 employers |
| Median days open | 42 d | 41 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $174k |
Skills observed across this category: post silicon validation, highspeed IO, PCI Express, CXL, AI GPU systems
Who's hiring in this category
- AMD (this employer) · 56 open roles · median 51 d
- Micron Technology · 41 open roles · median 35 d
- Qualcomm · 33 open roles · median 28 d
- Graphcore · 22 open roles · median 113 d
- NVIDIA · 21 open roles · median 28 d
- Microchip Technology · 20 open roles · median 66 d
How we counted: 401 open Post-Silicon Validation (Silicon Validation) roles from 63 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.