Physical Design Staff Engineer
Originally posted 30 September 2026 by the employer.
About the role
This role drives timing closure, signoff readiness, and PPA optimization for advanced-node customer designs, working across block, subsystem, and chip-level implementations. You will work on real silicon with real constraints, directly affecting whether customers can close their designs on time, especially at 3nm and 2nm nodes.
What you'll do
- Drive timing closure, signoff readiness, and PPA optimization for advanced-node customer designs
- Develop and enhance physical design methodologies and automation solutions using TCL, Python, Perl, or Pandas
- Perform static timing analysis, clock-tree synthesis, and ECO implementation using tools like PrimeTime, ICC2, Fusion Compiler, or Cadence Innovus
- Analyze design data and trends to identify bottlenecks and predict issues
- Collaborate with cross-functional engineering teams including design, verification, and CAD to ensure successful silicon delivery
- Contribute to AI-assisted and machine learning-driven design optimization initiatives
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
- 5+ years of hands-on experience with ASIC physical design, implementation, and timing closure across block, subsystem, or chip-level designs
- Deep working knowledge of static timing analysis, clock-tree synthesis, signoff flows, and ECO methodologies
- Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus
- Strong scripting and automation skills using TCL, Python, Perl, or similar languages
Nice to have
- Experience with advanced-node semiconductor design at 7nm or below
- Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows
Skills: timing closure, PPA optimization, ICC2, Fusion Compiler, static timing analysis
This role has been open 7 days — well below the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
671
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (671 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 671 |
| Open roles in the wider Physical Implementation family | 98 | 1485 · 107 employers |
| Median days open | 39 d | 60 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: timing closure, PPA optimization, ICC2, Fusion Compiler, static timing analysis
Who's hiring in this category
- Qualcomm · 130 open roles · median 38 d
- AMD · 59 open roles · median 21 d
- NVIDIA · 42 open roles · median 63 d
- Broadcom · 38 open roles · median 88 d
- Synopsys (this employer) · 35 open roles · median 39 d
- Micron Technology · 25 open roles · median 78 d
How we counted: 671 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.