Physical Design Signoff Engineer - Austin, United States
Originally posted 14 September 2026 by the employer.
This role focuses on building and enhancing Signoff dashboards, CAD flow metrics collection, and data visualization tools.
About the role
This role involves developing full-stack web applications for the Signoff infrastructure across all Apple SOC design groups within the Hardware Tech group, focusing on the critical final verification stage in chip design where designs are validated against manufacturing, timing, and power criteria before tapeout.
What you'll do
- Develop, support, and enhance Signoff dashboards, CAD flow metrics collection, and visualization tools.
- Build and maintain backend services and APIs.
- Develop interactive frontend dashboards.
- Work with SQL databases to manage and query enterprise-scale design data.
- Contribute to integrating RAG and AI-powered features to enhance how teams discover and interact with Signoff data.
- Provide Signoff infrastructure support and interface with design and CAD teams to develop high-impact web applications.
What you'll need
- BS in Computer Science or related field with 10+ years of relevant industry experience.
- Proficient in programming using Python, Perl, or Tcl.
- Hands-on experience with industry PNR and timing tools such as Cadence Innovus, Synopsys ICC2 / Fusion Compiler, PrimeTime, or Tempus.
- Experience taking block-level or chip-level designs through physical implementation and signoff closure on production silicon.
- Experience in timing closure, signal integrity, low-power design techniques, and clock-tree construction.
- Understanding of tradeoffs to meet PPA targets, and experience defining implementation recipes to improve PPA.
Nice to have
- Background in Chip Design, Chip Verification, or CAD.
- Experience with embedding models and LLM integration patterns.
- Understanding of RAG pipelines, including embeddings, chunking, and retrieval optimization.
- Experience with vector databases.
- Experience with containers and Kubernetes.
- Experience with monitoring and observability tools (Prometheus, Grafana).
- Test-driven development experience in production environments.
Skills: Signoff infrastructure, PNR and timing tools, physical implementation, timing closure, PPA
This role has been open 30 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
661
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (661 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 661 |
| Open roles in the wider Physical Implementation family | 29 | 1470 · 108 employers |
| Median days open | 23 d | 61 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Signoff infrastructure, PNR and timing tools, physical implementation, timing closure, PPA
Who's hiring in this category
- Qualcomm · 123 open roles · median 44 d
- AMD · 59 open roles · median 22 d
- NVIDIA · 39 open roles · median 69 d
- Synopsys · 37 open roles · median 29 d
- Broadcom · 34 open roles · median 94 d
- Intel Corporation · 30 open roles · median 12 d
How we counted: 661 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.