Physical Design (Multiple levels)
$115,600 - $173,400 USD yearly
Originally posted 9 August 2026 by the employer.
Contribute to the delivery of high-performance and power-efficient products.
About the role
You will participate in the complete physical design flow for sophisticated SoCs and IPs, including GPU, Camera, Multimedia, DDR, and Modem.
What you'll do
- Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
- Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
- Perform floorplanning, partitioning, power planning, and IR-drop analysis.
- Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
- Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
- Perform RC extraction, physical verification, and formal verification activities.
- Implement engineering change orders (ECOs) and support design convergence through sign-off.
- Collaborate with architecture, RTL, DFT, verification, and methodology teams.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 2 years of industry experience or relevant academic/project experience in Physical Design.
Nice to have
- Experience in ASIC/SoC Physical Design implementation.
- Experience with Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
- Experience with Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
- Experience with Physical verification and design sign-off methodologies.
- Experience with Formal verification techniques and tools.
- Experience with Power domain implementation and low-power design methodologies.
- Experience with Clock Tree Synthesis (CTS), routing, and timing optimization.
- Experience with Signal integrity, noise analysis, and MMMC sign-off flows.
- Experience with DFT-aware physical implementation and constraint management.
- Experience with Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
Skills: physical design, floorplanning, timing closure, place and route, MMMC, tape-out
This role has been open 69 days — well above the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
662
|
Median days open
59 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (662 roles · 81 employers) |
|---|---|---|
| Open roles in this specialty | 119 | 662 |
| Open roles in the wider Physical Implementation family | 161 | 1442 · 110 employers |
| Median days open | 44 d | 59 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: physical design, floorplanning, timing closure, place and route, MMMC, tape-out
Who's hiring in this category
- Qualcomm (this employer) · 119 open roles · median 44 d
- AMD · 63 open roles · median 23 d
- NVIDIA · 38 open roles · median 69 d
- Synopsys · 37 open roles · median 31 d
- Intel Corporation · 36 open roles · median 10 d
- Broadcom · 31 open roles · median 96 d
How we counted: 662 open Physical Design (Physical Design) roles from 81 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.