Physical Design Methodology Lead - Noida, India
Originally posted 29 September 2026 by the employer.
About the role
This role leads backend design automation for advanced process node SoC and ASIC implementation, focusing on enabling robust and scalable RTL-to-GDS flows.
What you'll do
- Own, develop, and improve backend RTL-to-GDS implementation flows for advanced process nodes.
- Drive methodology development across place and route, CTS, timing closure, congestion analysis, and signoff readiness.
- Partner with design, architecture, DFT, verification, timing, low-power, package, foundry, and signoff teams to meet tapeout requirements.
- Establish repeatable best practices, reference flows, automation frameworks, and metrics to improve PPA.
- Work with EDA vendors to evaluate and adopt new technologies in physical implementation and signoff.
- Debug complex flow, tool, constraint, timing, power, congestion, and physical verification issues.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
- 15+ years of experience in physical design, backend implementation, CAD, design automation, or flow and methodology development.
- Strong hands-on expertise with RTL-to-GDS implementation flows, including synthesis, floorplanning, placement, CTS, routing, optimization, extraction, timing closure, ECO, and physical verification.
- Deep understanding of timing signoff, constraints, STA debug, SDC methodology, multi-corner multi-mode closure, and setup/hold optimization.
- Experience with power grid design, IR drop, EM analysis, low-power implementation, multi-voltage design, UPF-based flows, and power optimization techniques.
- Strong scripting and automation skills using Tcl, Python, Perl, or shell scripting.
- Experience working with EDA platforms from Synopsys, Cadence, Siemens EDA, or equivalent tool ecosystems.
- Demonstrated ability to influence technical direction and drive cross-team initiatives.
Skills: physical design methodology, RTL-to-GDS implementation, timing closure, power integrity, EDA vendors
This role has been open 28 days — well below the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
682
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (682 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 682 |
| Open roles in the wider Physical Implementation family | 47 | 1507 · 111 employers |
| Median days open | 33 d | 66 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: physical design methodology, RTL-to-GDS implementation, timing closure, power integrity, EDA vendors
Who's hiring in this category
- Qualcomm · 126 open roles · median 49 d
- AMD · 61 open roles · median 29 d
- Intel Corporation · 40 open roles · median 19 d
- Synopsys · 38 open roles · median 41 d
- Broadcom · 37 open roles · median 102 d
- NVIDIA · 37 open roles · median 69 d
How we counted: 682 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.