Physical Design Methodology Engineer, AI HW IP - Austin, Texas, United States
$100,000 - $500,000 USD yearly
Originally posted 4 August 2026 by the employer.
This role develops, deploys, and owns the RTL-to-GDSII methodology for AI accelerators and high-performance RISC-V CPUs.
About the role
This role develops, deploys, and owns the RTL-to-GDSII methodology the IP physical design team runs on, ensuring new blocks, nodes, or customer variants start from a working flow.
What you'll do
- Develop and support physical design methodology or CAD flows in production use.
- Automate physical design steps to improve repeatability and PPA exploration.
- Build and integrate AI/ML-driven optimization into flow development.
- Partner with design teams and EDA vendors.
- Document flows clearly for independent team use.
What you'll need
- 5+ years developing and supporting physical design methodology or CAD flows.
- Expertise with FusionCompiler/ICC2, Innovus/Genus, PrimeTime, RedHawk.
- Expertise with Tcl, Python, Perl.
- Deep understanding of advanced node methodology, UPF/CPF, clock tree synthesis, EM/IR, DRC/LVS.
- Experience standing up flows for new technology nodes, PDKs, or foundry targets and qualifying new EDA releases.
Skills: physical design methodology, RTL-to-GDSII, advanced node methodology, UPF/CPF, FusionCompiler/ICC2
This role has been open 74 days — slightly above the 73-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
672
|
Median days open
73 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tenstorrent | All employers we track in this specialty (672 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 672 |
| Open roles in the wider Physical Implementation family | 12 | 1441 · 110 employers |
| Median days open | 39 d | 73 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: physical design methodology, RTL-to-GDSII, advanced node methodology, UPF/CPF, FusionCompiler/ICC2
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 170 d
- Synopsys · 63 open roles · median 36 d
- Micron Technology · 44 open roles · median 47 d
- Qualcomm · 36 open roles · median 75 d
- GlobalFoundries · 33 open roles · median 38 d
- Keysight Technologies · 32 open roles · median 72 d
How we counted: 672 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.