Physical Design Lead with STA - Hyderabad-Sattva, India
Originally posted 15 September 2026 by the employer — open 5 days.
This role focuses on SoC SS PD closure for high frequency CPU, HBM, DDR, Serdes interfaces.
About the role
This role involves owning and leading a SubSystem of 10 partitions, responsible for SoC SS Physical Design closure. The focus is on high frequency CPU, HBM, DDR, and Serdes interfaces from RTL to GDS execution.
What you'll do
- Own SubSystem Partitions PnR execution and closure.
- Drive new improvements in closure and analyze data for feedback to the Design team.
- Work with PnR team members for closure convergence from Synthesis to Route.
- Perform closure signoff on STA, EMIR, PV.
- Collaborate with business units, CAD, and central methodology teams to drive requirements.
- Implement automation to refine and improve design signoff requirements and dashboarding.
What you'll need
- 8+ years of experience in design signoff closure.
- Strong PnR background with critical problem-solving ability in improving PPA and debug.
- Technical depth in CTS, Route, STA.
- EMIR driven power grid knowledge.
- Experience with PnR and STA signoff correlation drive and convergence.
- Strong SDC coding and debug skills.
- Experience in scripting languages: TCL, Perl, Python, Makefile.
- Bachelors or Masters degree in Computer Engineering or Electrical Engineering.
Nice to have
- Experience in deploying and implementing ML techniques and algorithms in physical design.
- Experience with low power physical design implementation flows from RTL design through synthesis, place and route, timing closure, and physical verification.
- Experience with Synopsys, Cadence, and Mentor tools.
- Experience with AMD block TileBuilder.
- Experience in lower tech nodes (5/3/2).
Skills: PnR, STA, RTL to GDS, timing closure, physical verification
This role has been open 5 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
604
|
Median days open
59 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (604 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 604 |
| Open roles in the wider Physical Implementation family | 59 | 1373 · 107 employers |
| Median days open | 39 d | 59 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PnR, STA, RTL to GDS, timing closure, physical verification
Who's hiring in this category
- Qualcomm · 108 open roles · median 42 d
- NVIDIA · 39 open roles · median 44 d
- Broadcom · 38 open roles · median 69 d
- AMD (this employer) · 35 open roles · median 39 d
- Synopsys · 27 open roles · median 58 d
- Renesas Electronics · 25 open roles · median 46 d
How we counted: 604 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.