Physical Design Lead(High Speed IP's) - Bangalore-Technostar B1, India
Originally posted 3 September 2026 by the employer — open 7 days.
About the role
What you'll do
- Lead physical design implementation of complex high-speed IPs such as DDR/LPDDR/GDDR PHYs, PCIe, SerDes, and related subsystems.
- Own end-to-end implementation activities including Floorplanning, Power planning, Placement, Clock architecture, CTS, Timing closure, Signal integrity closure, Physical verification, and Tapeout signoff.
- Drive high-frequency timing closure for challenging datapaths and clock distribution networks.
- Partner with architects and circuit designers to optimize PHY architectures for performance, power, and implementation efficiency.
- Develop and deploy innovative implementation methodologies to improve design quality, productivity, and scalability.
- Mentor junior engineers and help grow the technical capability of the organization.
What you'll need
- 10+ years of industry experience in Physical Design for advanced semiconductor products.
- Proven track record delivering multiple successful tape-outs on advanced technology nodes (N3/N4/N5 or equivalent).
- Experience closing timing at aggressive frequencies and implementing complex clocking structures.
- Expertise with industry-standard EDA tools including Cadence and Synopsys implementation/signoff flows.
- Experience driving methodology development and automation.
- Demonstrated leadership across cross-functional teams and geographies.
- BS/MS in Electrical Engineering, Computer Engineering, VLSI Design, or related field.
Nice to have
- AI-assisted Design Flows
Skills: High Speed IP's, DDR/LPDDR/GDDR PHYs, PCIe, SerDes, high-frequency timing closure
This role has been open 7 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 35 | 1317 · 100 employers |
| Median days open | 61 d | 91 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: High Speed IP's, DDR/LPDDR/GDDR PHYs, PCIe, SerDes, high-frequency timing closure
Who's hiring in this category
- AMD (this employer) · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.