Physical Design Lead — Execution - San Jose, California, United States
$231,500 - $341,075 USD yearly
Originally posted 21 September 2026 by the employer.
About the role
This role drives day-to-day physical design execution and delivery for Altera chips from floorplan through tapeout. The role focuses on block and full-chip closure, ensuring schedule and quality under pressure.
What you'll do
- Drive day-to-day physical design execution and delivery across blocks and full-chip integration, from floorplan through tapeout.
- Own the schedule and quality bar for physical design execution, proactively identifying risk and driving mitigation.
- Coordinate execution across multiple blocks and design teams, resolving conflicts and dependencies for full-chip closure.
- Engage senior customer technical stakeholders directly, navigating challenging technical conversations with credibility, diplomacy, and influence.
- Serve as the escalation point for execution blockers, driving fast, pragmatic resolution under schedule pressure.
- Mentor physical design engineers on execution best practices, prioritization, and schedule management.
What you'll need
- Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years (Sr. Principal Engineer) or 12+ years (Principal Engineer) of physical design experience, including a minimum of four full-chip tapeouts at advanced nodes with direct execution ownership.
- Hands-on expertise across the physical design flow: floorplanning, placement, clock-tree synthesis, routing, and timing/power closure.
- Hands-on proficiency with industry-standard implementation and signoff tools (Synopsys Fusion Compiler / ICC2 / PrimeTime, Cadence Innovus / Tempus / Voltus, Ansys RedHawk-SC, Siemens Calibre, or equivalent).
- Working command of horizontal signoff flows: timing closure (STA), EMIR, physical verification, formal equivalence, and low-power verification.
- Scripting and automation proficiency (Python, Tcl, Perl, or shell) to build and debug execution tooling.
Nice to have
- Experience serving as an implementation lead or execution owner for a full chip or major subsystem.
- Direct experience representing physical design execution in customer-facing technical reviews.
- Working familiarity with PD signoff methodology (EMIR, timing, power) sufficient to partner effectively with methodology teams.
- Experience mentoring or informally leading execution teams without formal management authority.
Skills: physical design, floorplan, timing closure, tapeout, signoff
This role has been open 20 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (673 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 673 |
| Open roles in the wider Physical Implementation family | 27 | 1475 · 107 employers |
| Median days open | 88 d | 61 d (+27 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical design, floorplan, timing closure, tapeout, signoff
Who's hiring in this category
- Qualcomm · 126 open roles · median 43 d
- AMD · 62 open roles · median 19 d
- NVIDIA · 41 open roles · median 65 d
- Broadcom · 35 open roles · median 90 d
- Synopsys · 35 open roles · median 41 d
- Intel Corporation · 29 open roles · median 11 d
How we counted: 673 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.