Physical Design Engineer- Staff to Sr. Staff - Austin, Texas, United States of America, United States

Originally posted 29 September 2026 by the employer.

This role focuses on advanced clocking solutions for NSP designs.

About the role

The work focuses on high-performance clock architecture and implementation for ASICs and SoCs.

What you'll do

• Own and drive clock physical design methodology, implementation, optimization, and signoff for complex NSP designs.
• Architect, implement, and optimize advanced clock distribution structures, including Clock H-trees, Clock mesh architectures, Clock spine methodologies, hierarchical clock distribution, clock gating, and low-power clock distribution techniques.
• Analyze and debug clock-related timing and clock skew, dynamic and leakage power, signal integrity and noise, on-chip variation, jitter and clock uncertainty, duty-cycle distortion, slew and waveform degradation, and physical implementation and routing issues.
• Drive clock convergence and signoff across multiple modes, process corners, voltage conditions, temperatures, and operating frequencies.
• Perform detailed clock timing analysis using Synopsys PrimeTime and correlate implementation, STA, extraction, and SPICE results.
• Develop and enhance clock analysis, debug, characterization, and implementation automation using TCL, Python, Perl, and Linux shell scripting.

What you'll need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 10 years of industry experience in ASIC/SoC Physical Design with significant hands-on experience in high-performance clock implementation and timing closure.
• Deep hands-on expertise with advanced clock distribution methodologies, including Clock H-trees, Clock mesh, Clock spines, hierarchical clock distribution, clock gating, and low-power clock implementation.
• Strong understanding of clock skew and insertion delay, jitter and clock uncertainty, slew and duty-cycle distortion, PVT and on-chip variation, clock power optimization, clock signal integrity, clock-related IR/EM concerns, and multi-mode/multi-corner timing analysis.
• Hands-on experience with SPICE simulation and the ability to analyze clock circuits and distribution structures at the transistor and waveform level.
• Strong experience with industry-standard Physical Design and signoff tools, including Synopsys Fusion Compiler / ICC2 and/or Cadence Innovus, Synopsys PrimeTime, RC extraction and signal-integrity analysis tools, and physical verification and DRC/LVS signoff flows.
• Proficiency in TCL, Python, Perl, and Linux/Unix environments.

Nice to have

• Experience developing and deploying custom clock methodologies for high-frequency designs.
• Experience with advanced technology nodes and clock-design challenges associated with increased process variation, interconnect resistance, power density, and reduced voltage margins.
• Strong understanding of PLL behavior, jitter, clock-source modeling, and clock uncertainty budgeting.
• Familiarity with Infinisim or PrimeClock.
• Knowledge of dynamic power, IR-drop, electromigration, signal integrity, crosstalk, and reliability analysis as they relate specifically to high-performance clock networks.
• Experience working across hierarchical SoC implementation, including interaction between clock source, top-level clock distribution, and block-level clock networks.

Skills: clock physical design, clock distribution structures, timing closure, Synopsys PrimeTime, ASIC/SoC Physical Design