Physical Design Engineer, Staff - Austin, Texas, United States of America, United States
$145,600 - $218,400 USD yearly
Originally posted 24 September 2026 by the employer.
About the role
This Staff Physical Design Engineer role involves defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) development.
What you'll do
- Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development.
- Create advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
- Collaborate with functional teams to develop and execute an implementation strategy that meets system requirements and customer needs.
- Evaluate complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
- Utilize tools/applications such as RTL to GDS Flow and Virtuoso to execute advanced architecture and design of multiple complex blocks/SoC or IC Packages.
- Write and review detailed technical documentation for complex EDA/IP/ASIC projects.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field and 4+ years of ASIC design, verification, validation, integration, or related work experience; OR Master's degree in Science, Engineering, or a related field and 3+ years of ASIC design, verification, validation, integration, or related work experience; OR PhD in Science, Engineering, or a related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 6 years of ASIC design, verification, validation, integration, or related work experience.
- 2 years of experience with architecture and design tools.
- 2 years of experience with scripting tools and programming languages.
- 2 years of experience with design verification methods.
- 1 year of work experience in a role requiring interaction with senior leadership.
Skills: ASIC design, place and route, timing and power use, RTL to GDS Flow, IP (block/SoC) development
This role has been open 16 days — well below the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
683
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (683 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 126 | 683 |
| Open roles in the wider Physical Implementation family | 175 | 1473 · 107 employers |
| Median days open | 42 d | 60 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC design, place and route, timing and power use, RTL to GDS Flow, IP (block/SoC) development
Who's hiring in this category
- Qualcomm (this employer) · 131 open roles · median 39 d
- AMD · 62 open roles · median 18 d
- NVIDIA · 42 open roles · median 64 d
- Broadcom · 36 open roles · median 89 d
- Synopsys · 35 open roles · median 40 d
- Intel Corporation · 29 open roles · median 10 d
How we counted: 683 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.