Physical Design Engineer - San Jose, California, United States

Originally posted 12 August 2026 by the employer.

About the role

This role involves contributing to the implementation of custom IP and SoC designs from RTL through GDSII, supporting timing closure, power optimization, physical verification, and design signoff for semiconductor products.

What you'll do

• Perform block-level physical design implementation of custom IP and SoC designs from RTL through GDSII.
• Execute and support stages of the physical design flow, including synthesis, floorplanning, power planning, place and route, clock tree synthesis (CTS), timing analysis, and physical optimization.
• Perform static timing analysis (STA) and help resolve setup, hold, signal integrity, and other timing violations.
• Participate in physical verification and signoff activities, including formal equivalence checking (LEC), static timing analysis, power integrity, IR drop, electromigration (EM), layout verification, electrical rule checking (ERC), design rule checking (DRC), layout versus schematic (LVS), and structural verification.
• Analyze physical design results, identify root causes of implementation issues, and implement corrective actions.
• Contribute to the development, enhancement, and automation of physical design methodologies, flows, and infrastructure.

What you'll need

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline and 3+ years of experience in semiconductor Physical Design.
• 3+ years of experience with physical design implementation of custom IP or SoC designs from RTL through GDSII.
• 3+ years of experience with physical design flows including synthesis, floorplanning, place and route, clock tree synthesis (CTS), and physical optimization.
• 2+ years of experience performing static timing analysis (STA) and supporting timing closure on semiconductor designs.
• 2+ years of experience with physical verification and signoff activities, including DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and/or power integrity analysis.

Nice to have

• Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Experience with advanced technology nodes (7nm, 5nm, 3nm, or smaller).
• Experience implementing high-performance CPU, FPGA, AI accelerator, networking, or SoC designs.
• Experience with Tcl, Python, Perl, or Shell scripting for flow automation.
• Knowledge of static timing analysis and low-power implementation methodologies, including UPF/CPF.
• Experience with Synopsys, Cadence, or Siemens EDA physical design and analysis tools.

Skills: physical design implementation, RTL through GDSII, timing closure, place and route, static timing analysis, DRC LVS ERC