Physical Design Engineer - Remote
$180,000 - $260,000 USD yearly
Originally posted 10 September 2026 by the employer.
About the role
As a Physical Design Engineer, you will own challenging physical implementation problems in design, drive critical blocks and top-level integration, and establish methodologies for performance, power, area, and schedule targets. This hands-on role involves taking complex designs from floorplan through signoff, solving difficult timing and implementation problems, and providing technical leadership.
What you'll do
- Own physical implementation of complex blocks and subsystems from synthesized netlist through signoff.
- Develop floorplans considering hierarchy, macros, interfaces, congestion, timing, power, and routability.
- Drive placement, optimization, clock-tree synthesis, routing, extraction, timing closure, and ECO implementation.
- Lead timing closure across block boundaries and support top-level timing convergence.
- Drive physical signoff, including DRC, LVS, antenna, density, connectivity, and related physical verification requirements.
- Develop and improve physical design flows, scripts, automation, metrics, and methodologies.
What you'll need
- 10+ years of ASIC or SoC physical design experience with multiple successful tapeouts.
- Expert-level understanding of floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification.
- Strong expertise in static timing analysis and multi-mode, multi-corner timing closure.
- Strong understanding of power delivery, IR drop, electromigration, and signal integrity.
- Experience with industry-standard Cadence and/or Synopsys physical implementation and signoff tools.
- Strong scripting and automation skills using Tcl, Python, Perl, or similar languages.
Nice to have
- Experience with advanced process nodes.
- Experience with large, high-frequency or highly interconnected semiconductor designs.
- Experience with hierarchical design and top-level physical integration.
- Experience developing physical design methodologies and automation.
- Experience with multi-die, chiplet, or advanced packaging architectures.
Skills: floorplanning, timing closure, physical verification, IR-drop
This role has been open 36 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
662
|
Median days open
59 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Delos Data | All employers we track in this specialty (662 roles · 81 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 662 |
| Open roles in the wider Physical Implementation family | 1 | 1443 · 110 employers |
| Median days open | 36 d | 59 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: floorplanning, timing closure, physical verification, IR-drop
Who's hiring in this category
- Qualcomm · 119 open roles · median 44 d
- AMD · 63 open roles · median 23 d
- NVIDIA · 38 open roles · median 69 d
- Synopsys · 37 open roles · median 31 d
- Intel Corporation · 36 open roles · median 10 d
- Broadcom · 31 open roles · median 96 d
How we counted: 662 open Physical Design (Physical Design) roles from 81 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.