Physical Design Engineer II (eInfochips Inc) - US-CA-San Jose, California, United States
Originally posted 9 July 2026 by the employer. Relisted by the employer on 7 August 2026.
Execute synthesis, PNR, and STA using Innovus, Tempus, and Quantus.
About the role
Arrow Electronics is seeking a Physical Design Engineer II (eInfochips Inc) based on-site in San Jose, California to execute synthesis, PNR, and STA for assigned ASIC chip partitions.
What you'll do
- Execute synthesis, PNR, and STA for assigned partitions of ASIC chips adhering to schedules and design goals. - Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across assigned blocks. - Close EM/IR, drive LEC, and achieve physical verification signoff for assigned partitions in coordination with methodology owners. - Partner with the design team to proactively identify and address physical design challenges for iteration and convergence. - Contribute to the refinement of implementation methodologies spanning synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). - Troubleshoot flow issues and collaborate with EDA vendors to resolve them.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience. - 7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence, and physical verification. - Proficiency in Electronic Design Automation (EDA) tools including Innovus, Tempus, and Quantus. - Deep understanding of physical design flows and methodologies.
Nice to have
- Low-power design techniques implementation experience. - Experience in System-on-Chip (SoC) design and implementation. - Expertise in sub-7nm node technologies. - Scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.
Skills: Physical design, PNR, STA, EM/IR, LEC
This role has been open 103 days — well above the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
656
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arrow Electronics | All employers we track in this specialty (656 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 656 |
| Open roles in the wider Physical Implementation family | 4 | 1441 · 110 employers |
| Median days open | 97 d | 61 d (+36 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Physical design, PNR, STA, EM/IR, LEC
Who's hiring in this category
- Qualcomm · 119 open roles · median 44 d
- AMD · 61 open roles · median 26 d
- Synopsys · 38 open roles · median 35 d
- Intel Corporation · 36 open roles · median 14 d
- NVIDIA · 36 open roles · median 70 d
- Broadcom · 32 open roles · median 100 d
How we counted: 656 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.