Physical Design Engineer - Full Chip Implementation - San Jose, United States
Originally posted 23 July 2026 by the employer.
About the role
As a top-level Physical Design Engineer, you will own full-chip implementation from synthesis through to GDSII completion, including floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs.
What you'll do
- Own full-chip clocking across all PVT corners and modes. - Manage MMMC (Multi-Mode Multi-Corner) timing closure, timing constraints, and hierarchical timing budgeting between top level and blocks. - Drive functional and timing ECO closure to achieve final timing signoff for tapeout. - Own end-to-end physical verification closure across DRC, LVS, ERC, antenna, density, fill, and top-level integration at block, sub-system, and full-chip levels. - Debug complex PV violations across layout, routing, macros, IP, power grid, and rule decks, fixing violations directly in layout using Cadence Innovus. - Build a repeatable, tapeout-ready PV methodology covering clean runs, waiver discipline, version control, triage, and final signoff reviews.
What you'll need
- 10+ years of experience with chip planning, top level PD, and floorplanning. - Experience with top-level and full-chip closure on advanced process nodes (5nm and below). - Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows. - Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff. - Experience with Pegasus or Calibre for physical verification signoff. - Experience with hierarchical timing budgeting, constraint management, and ECO closure.
Skills: full-chip clocking, MMMC timing closure, physical verification, tapeout, advanced process nodes, Cadence Innovus
This role has been open 88 days — well above the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 659 |
| Open roles in the wider Physical Implementation family | 8 | 1441 · 109 employers |
| Median days open | 88 d | 61 d (+27 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: full-chip clocking, MMMC timing closure, physical verification, tapeout, advanced process nodes, Cadence Innovus
Who's hiring in this category
- Qualcomm · 119 open roles · median 46 d
- AMD · 63 open roles · median 25 d
- Intel Corporation · 37 open roles · median 12 d
- Synopsys · 37 open roles · median 33 d
- NVIDIA · 36 open roles · median 71 d
- Broadcom · 30 open roles · median 98 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.