Physical Design Engineer
$159,600 - $239,400 USD yearly
Originally posted 29 October 2026 by the employer.
About the role
Physical Design Engineers in this role execute physical design for ASIC and SoC development from synthesized netlist through tape-out. Technical focus areas include floorplanning, Clock Tree Synthesis, low-power implementation, timing analysis, design methodology, and automation across advanced process technologies.
What you'll do
- Execute all stages of the physical design flow from synthesized netlist to tape-out for complex, high-speed, and low-power ASICs and SoCs.
- Perform floorplanning, partitioning, power planning, and IR-drop analysis.
- Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
- Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
- Perform RC extraction, physical verification, formal verification, and engineering change orders (ECOs) through sign-off.
- Develop automation and productivity tools using scripting languages and software development techniques.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 4+ years of relevant experience, a Master's degree with 3+ years, or a PhD with 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Experience executing physical design flow stages including synthesized netlist handling, floorplanning, and timing convergence.
- Knowledge of timing analysis, signal integrity, and physical verification activities.
Nice to have
- Place and Route experience using Cadence Innovus and/or Synopsys Fusion Compiler.
- Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
- Clock Tree Synthesis (CTS), routing, and timing optimization experience.
- Experience with power domain implementation, low-power design methodologies, and low-power implementation techniques.
- Signal integrity, noise analysis, and MMMC sign-off flows.
- Programming and automation skills in Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
Skills: Floorplanning, CTS, Place and Route, Innovus, PrimeTime
More semiconductor jobs: Qualcomm jobs · Physical design jobs · Santa Clara jobs
This role has been open 0 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
688
|
Median days open
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (688 roles · 82 employers) |
|---|---|---|
| Open roles in this specialty | 111 | 688 |
| Open roles in the wider Physical Implementation family | 155 | 1536 · 112 employers |
| Median days open | 51 d | 59 d (−8 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Floorplanning, CTS, Place and Route, Innovus, PrimeTime
Who's hiring in this category
- Qualcomm (this employer) · 109 open roles · median 53 d
- AMD · 63 open roles · median 32 d
- Synopsys · 39 open roles · median 44 d
- Intel Corporation · 38 open roles · median 22 d
- Broadcom · 37 open roles · median 100 d
- NVIDIA · 37 open roles · median 69 d
How we counted: 688 open Physical Design (Physical Design) roles from 82 employers tracked in the SemiconductorJobs index, counted 30 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.