Physical Design Engineer - Block Level, Subsystem Implementation - San Jose, United States
Originally posted 23 July 2026 by the employer.
About the role
As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off and drive block-level and subsystem PPA optimization. You will collaborate closely with RTL designers to provide actionable feedback on hardware targeting frontier inference workloads.
What you'll do
- Own block-level and subsystem physical design end-to-end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII. - Drive block-level timing closure across all corners and modes, covering constraint development, STA debug, and functional and timing ECO implementation. - Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification including DRC, LVS, and antenna. - Generate abstracts, views, and timing budgets for clean hierarchical integration of blocks into the top level. - Collaborate with RTL designers to provide physical design feedback and continuously optimize PPA. - Supervise physical design work outsourced to third-party services and take accountability for the quality and closure of delivered blocks.
What you'll need
- 5-10+ years of physical design experience across tools, flows, and methodology from RTL synthesis to GDSII sign-off. - Experience with back-end design and timing closure on advanced process nodes (5nm and below). - Hands-on experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows. - Experience with sign-off tools such as PrimeTime, Tempus, or Voltus. - Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis. - Scripting proficiency in Tcl, Python, or Perl for flow automation and debug.
Skills: floorplanning, CTS, routing, timing closure, GDSII, advanced process nodes
This role has been open 88 days — well above the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 659 |
| Open roles in the wider Physical Implementation family | 8 | 1441 · 109 employers |
| Median days open | 88 d | 61 d (+27 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: floorplanning, CTS, routing, timing closure, GDSII, advanced process nodes
Who's hiring in this category
- Qualcomm · 119 open roles · median 46 d
- AMD · 63 open roles · median 25 d
- Intel Corporation · 37 open roles · median 12 d
- Synopsys · 37 open roles · median 33 d
- NVIDIA · 36 open roles · median 71 d
- Broadcom · 30 open roles · median 98 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.