Physical Design Engineer - Block Level, Subsystem Implementation - Austin, United States
Originally posted 30 July 2026 by the employer.
Etched is building hardware for frontier intelligence, with a focus on inference.
About the role
As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off. You will drive Block-level & Subsystem PPA Optimization on advanced process nodes (5nm and below).
What you'll do
- Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII.
- Drive block-level timing closure across all corners and modes, including constraint development, STA debug, and functional and timing ECO implementation.
- Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification (DRC, LVS, antenna).
- Generate abstracts, views, and timing budgets for clean hierarchical integration of blocks into the top level.
- Collaborate with RTL Designers and provide Physical Design feedback to improve PPA.
- Supervise physical design work outsourced to 3rd party services and be accountable for the quality and closure of delivered blocks.
What you'll need
- 5-10+ years of previous experience with Physical Design.
- Experience with tools, flow, and design methodology from RTL synthesis to GDSII sign-off.
- Experience with back-end design and timing closure on advanced process nodes (5nm and below).
- Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows.
- Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.).
- Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis.
- Scripting ability in Tcl, Python, or Perl for flow automation and debug.
Skills: floorplanning, synthesis, placement, clock tree synthesis, GDSII, timing closure
This role has been open 80 days — well above the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
60 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 659 |
| Open roles in the wider Physical Implementation family | 8 | 1441 · 110 employers |
| Median days open | 87 d | 60 d (+27 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: floorplanning, synthesis, placement, clock tree synthesis, GDSII, timing closure
Who's hiring in this category
- Qualcomm · 119 open roles · median 45 d
- AMD · 63 open roles · median 24 d
- NVIDIA · 37 open roles · median 72 d
- Synopsys · 37 open roles · median 32 d
- Intel Corporation · 36 open roles · median 11 d
- Broadcom · 30 open roles · median 97 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.