Physical Design Engineer
$190,200 - $285,400 USD yearly
Originally posted 14 October 2026 by the employer.
About the role
This role involves physical design for SoC and ASIC development, contributing to projects in high-performance computing, AI, mobile, automotive, and data center. You will work on different aspects of physical design, including floorplan, Clock Tree Synthesis, timing analysis, and enabling new technology nodes.
What you'll do
- Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
- Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
- Perform floorplanning, partitioning, power planning, and IR-drop analysis.
- Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
- Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
- Perform RC extraction, physical verification, and formal verification activities.
- Implement engineering change orders (ECOs) and support design convergence through sign-off.
- Collaborate with architecture, RTL, DFT, verification, and methodology teams.
- Contribute to the development of low-power implementation methodologies and customized place-and-route solutions.
- Develop automation and productivity tools using scripting languages and software development techniques.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 10 years of industry experience or relevant academic/project experience in Physical Design.
Nice to have
- Experience in ASIC/SoC Physical Design implementation.
- Experience with Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
- Experience with Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
- Experience with Physical verification and design sign-off methodologies.
- Experience with Formal verification techniques and tools.
- Experience with Power domain implementation and low-power design methodologies.
- Experience with Clock Tree Synthesis (CTS), routing, and timing optimization.
- Experience with Low power implementation techniques.
- Experience with Signal integrity, noise analysis, and MMMC sign-off flows.
- Experience with DFT-aware physical implementation and constraint management.
- Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
- Strong problem solving and ASIC development/debugging skills.
Skills: Physical Design, floorplan, Clock Tree Synthesis, timing analysis, place and route, physical verification
This role has been open 0 days — well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
664
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (664 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 123 | 664 |
| Open roles in the wider Physical Implementation family | 170 | 1463 · 108 employers |
| Median days open | 44 d | 63 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Physical Design, floorplan, Clock Tree Synthesis, timing analysis, place and route, physical verification
Who's hiring in this category
- Qualcomm (this employer) · 122 open roles · median 46 d
- AMD · 59 open roles · median 21 d
- NVIDIA · 39 open roles · median 68 d
- Broadcom · 35 open roles · median 93 d
- Synopsys · 35 open roles · median 44 d
- Intel Corporation · 29 open roles · median 14 d
How we counted: 664 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.