Physical Design Engineer (AS-64000921) - Austin, Texas, United States
$3 USD yearly
Originally posted 6 March 2026 by the employer.
Deliver complete RTL to GDSII implementation on mixed-signal SoCs at 40nm, 28nm, and below.
About the role
Cirrus Logic is looking for a Physical Design Engineer to join its Implementation team responsible for physical implementation from RTL to GDSII. You will work on mixed-signal SoC designs for consumer mobile audio markets.
What you'll do
- Execute physical implementation from RTL to GDSII, including RTL synthesis and scan stitching. - Develop placement and route structures for complete ASIC designs and analyze clock distribution on full-chip assembly. - Define and debug timing constraints, perform Static Timing Analysis, and run timing closure, ECO generation, and tape-out down to 40nm, 28nm, and below. - Analyze power constraints, chip floor plan, and perform IR Drop analysis and improvement. - Automate and advance physical design flows and tool evaluation using Perl and Tcl scripting.
What you'll need
- Bachelor's or Master's in Electrical Engineering and 3+ years of industry experience in a Logic design or Physical Design position. - Understanding of RTL design, with familiarity in Cadence Genus/Innovus and Synopsys Design Compiler/ICC/Fusion Compiler. - Experience with PrimeTime, Conformal LEC, and ATPG. - Solid understanding of scan insertion and ATPG.
Nice to have
- Experience participating in design and architecture reviews. - Background defining physical design methodologies and flow automation. - Ability to perform debug and analysis for designs, library, and technology files. - Experience providing mentorship and guidance to junior engineers.
Skills: RTL to GDSII, RTL synthesis, timing optimization, floorplan, Static Timing Analysis, IR Drop analysis
This role has been open 220 days — well above the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
676
|
Median days open
66 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cirrus Logic | All employers we track in this specialty (676 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 676 |
| Open roles in the wider Physical Implementation family | 6 | 1513 · 111 employers |
| Median days open | 189 d | 66 d (+123 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: RTL to GDSII, RTL synthesis, timing optimization, floorplan, Static Timing Analysis, IR Drop analysis
Who's hiring in this category
- Qualcomm · 123 open roles · median 49 d
- AMD · 63 open roles · median 28 d
- Intel Corporation · 40 open roles · median 18 d
- Synopsys · 37 open roles · median 40 d
- NVIDIA · 36 open roles · median 68 d
- Broadcom · 35 open roles · median 105 d
How we counted: 676 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.