$101,400 - $152,200 USD yearly
Originally posted 13 September 2026 by the employer.
Develop IP (block/SoC) for high performance, high quality, low power products.
About the role
As a Physical Design Engineer, you will assist in the definition, design, optimization, verification, and implementation of IP (block/SoC) development for various products. This role focuses on the evaluation of process flow from high-level design through synthesis, place and route, timing and power analysis, and verification.
What you'll do
- Apply ASIC knowledge to assist in defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) development.
- Assist in the creation of architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
- Collaborate with team members to assist in developing an implementation strategy that meets system requirements and customer needs.
- Support the evaluation of process flow from high-level design to synthesis, place and route, and timing and power use, and verification.
- Utilize tools/applications such as RTL to GDS Flow and Virtuoso to execute and enable architecture and design of a specific part of a block/SoC or IC Package.
- Write technical documentation for EDA/IP/ASIC projects.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 6 months of experience with architecture and design tools.
- 6 months of experience with scripting tools and programming languages.
- 6 months of experience with design verification methods.
Skills: ASIC, RTL to GDS Flow, place and route, timing, power
This role has been open 32 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
661
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (661 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 124 | 661 |
| Open roles in the wider Physical Implementation family | 171 | 1469 · 108 employers |
| Median days open | 44 d | 61 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC, RTL to GDS Flow, place and route, timing, power
Who's hiring in this category
- Qualcomm (this employer) · 123 open roles · median 44 d
- AMD · 59 open roles · median 22 d
- NVIDIA · 39 open roles · median 69 d
- Synopsys · 37 open roles · median 29 d
- Broadcom · 34 open roles · median 94 d
- Intel Corporation · 30 open roles · median 12 d
How we counted: 661 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.