Physical Design and Signoff, Sr. Principal AE - San Jose, United States
$148,400 - $275,600 USD yearly
Originally posted 21 October 2026 by the employer.
About the role
This role provides technical support and customer engagement for digital implementation and signoff flows across Synthesis, Place and Route, and timing/power closure. You will work directly with customer engineering teams and Cadence R&D to meet PPA targets and improve EDA tool flows.
What you'll do
- Provide technical support to customers in backend digital design implementation and signoff, including Place and Route, design closure, and timing/power signoff. - Guide customers on deploying Cadence technologies to reach design closure goals and schedule requirements. - Collaborate with the team to deliver technical presentations and product demonstrations. - Drive customer technical evaluations and benchmarks to completion. - Work directly with Cadence R&D to enhance tools and methodologies based on customer requirements. - Amend and augment implementation flows using Tcl and other scripting skills. - Capture best practices and lessons learned from benchmarks to apply to future customer engagements.
What you'll need
- 10+ years of industry Physical Design experience. - BS degree in Computer Science/Engineering, Electrical Engineering, or a related field. - Background in digital design fundamentals, semiconductor fundamentals, and static timing analysis. - Experience with IC digital implementation flows and backend EDA tools, including Place and Route, IR Drop, and backend timing and power closure. - Hands-on experience with advanced process nodes at 10nm and below. - Scripting proficiency in Tcl, Perl, or Python.
Nice to have
- MS degree in Computer Science/Engineering, Electrical Engineering, or a related field. - Experience with front-end EDA tools and flows including Synthesis, DFT, and Logical Equivalence Checking. - Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus, or equivalent tools including ICC, ICC2, DC, or PrimeTime. - Experience with advanced process nodes at 5nm and below.
Skills: Field Applications, Place and Route, STA, IR Drop, Tcl
This role has been open 0 days — well below the 33-day median for Applications FAE roles.
Applications FAE · EDA Tools
|
Open roles in category
111
|
Median days open
33 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (111 roles · 11 employers) |
|---|---|---|
| Open roles in this specialty | 31 | 111 |
| Median days open | 27 d | 33 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Skills observed across this category: Field Applications, Place and Route, STA, IR Drop, Tcl
Who's hiring in this category
- Synopsys · 60 open roles · median 30 d
- Cadence Design Systems (this employer) · 25 open roles · median 35 d
- Keysight Technologies · 9 open roles · median 55 d
- Renesas Electronics · 9 open roles · median 68 d
- Arteris · 2 open roles · median 120 d
- Amazon · 1 open role · median 21 d
How we counted: 111 open Applications FAE (EDA Tools) roles from 11 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.