Photonic Mixed Signal Design Validation Engineer - CA, Santa Clara, United States
Originally posted 17 August 2026 by the employer. Relisted by the employer on 18 August 2026.
Validate and debug co-packaged optics (CPO) products for the Mixed-Signal Compose group.
About the role
As a Photonic Mixed Signal Design Validation Engineer, you will develop and debug co-packaged optics (CPO) products. You will define test methods and characterize builds for the Mixed-Signal Compose group.
What you'll do
- Develop validation test methods for new photonic builds from the Mixed-Signal Compose group.
- Characterize fundamental optical, electro-optical, and RF performance of new chip builds.
- Validate, debug, and characterize new analog, photonic, electrical-optical, and mixed-signal builds.
- Provide feedback to designers on silicon performance, build quality, and margins.
- Verify electrical-optical compliance to industry standards.
- Interact with multi-functional groups to support chip development and validation.
What you'll need
- Master of Science in Electrical Engineering, Physics, Computer Engineering, or equivalent experience.
- 2+ years of experience measuring, analyzing, and debugging complex mixed-signal builds.
- Deep understanding of fundamental optical components and analog circuits.
- RF testing experience at die or module level.
- Experience with Python, Git, Matlab, or JMP, including coding scripts for validation, debug, data analysis, and automation.
- Detailed knowledge of optical lab equipment.
Skills: photonic mixed signal, co-packaged optics (CPO), validation test methods, optical components, analog circuits, RF testing
This role has been open 200 days — well above the 37-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
563
|
Median days open
37 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (563 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 563 |
| Open roles in the wider Silicon Validation & Test family | 85 | 2235 · 112 employers |
| Median days open | 57 d | 37 d (+20 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Skills observed across this category: photonic mixed signal, co-packaged optics (CPO), validation test methods, optical components, analog circuits, RF testing
Who's hiring in this category
- Teradyne · 75 open roles · median 29 d
- Infineon Technologies · 46 open roles · median 41 d
- Renesas Electronics · 44 open roles · median 31 d
- Qualcomm · 31 open roles · median 37 d
- Micron Technology · 28 open roles · median 41 d
- Texas Instruments · 28 open roles · median 32 d
How we counted: 563 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.