Ph.D. Intern - Architecture, DSP & Systems Architecture - United States
$31 - $62 USD yearly
Originally posted 10 September 2026 by the employer — open 0 days.
The architecture decisions for Marvell's Teralynx Ethernet switch family define what AI infrastructure can do.
About the role
This role involves solving systems-level problems at the intersection of research and production in architecture, DSP, and systems architecture. The work will focus on AI interconnect hierarchy, including scale-up networks, scale-out fabrics with the Teralynx Ethernet switch family, and scale-across connectivity with coherent DSP and DCI platforms.
What you'll do
- Architect, model, and evaluate system-level designs for switching, interconnect, or DSP applications.
- Develop and optimize DSP algorithms for high-speed electrical or optical links.
- Design and analyze network architectures for AI fabrics.
- Collaborate with analog, digital, and software engineering teams to validate architectural assumptions.
- Build behavioral models and simulations in MATLAB, Python, or C++ to evaluate performance tradeoffs.
- Present architectural proposals and algorithm results to engineering leadership and contribute to internal technical documentation and design reviews.
What you'll need
- Currently enrolled in a Ph.D. program in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with a research focus in computer architecture, digital signal processing, communications systems, or networking.
- Research experience in one or more of the following: processor or switch architecture, DSP algorithm design for high-speed communications, network protocol design, or system-level modeling and simulation.
- Strong analytical fundamentals in signal processing theory, queuing theory, information theory, or computer architecture.
- Experience modeling and simulating complex systems using tools such as MATLAB, Python, or C/C++.
- Ability to communicate architectural decisions and algorithm tradeoffs clearly.
Nice to have
- Familiarity with Ethernet switching architectures, programmable forwarding pipelines, or network congestion control algorithms for large-scale AI fabrics.
- Experience with PAM4, coherent, or high-speed serial link DSP, including equalization, FEC, or timing and synchronization algorithms.
- Exposure to custom compute architecture, SoC design, or XPU/GPU interconnect systems.
- Knowledge of Ultra Ethernet Consortium (UEC) protocols, RoCE, or RDMA networking for AI workloads.
- Experience with open networking platforms such as SONiC or P4-based programmable pipelines.
- Familiarity with hardware description languages (Verilog, SystemVerilog) or cycle-accurate simulation.
Skills: AI interconnect hierarchy, Teralynx Ethernet switch, DSP algorithms, co-packaged optics, systems architects
This role has been open 0 days — well below the 69-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
450
|
Median days open
69 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (450 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 450 |
| Open roles in the wider Digital Design & Verification family | 117 | 3033 · 114 employers |
| Median days open | 133 d | 69 d (+64 d vs this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: AI interconnect hierarchy, Teralynx Ethernet switch, DSP algorithms, co-packaged optics, systems architects
Who's hiring in this category
- Qualcomm · 68 open roles · median 72 d
- NVIDIA · 54 open roles · median 50 d
- AMD · 32 open roles · median 63 d
- Arm Holdings · 27 open roles · median 77 d
- Renesas Electronics · 20 open roles · median 77 d
- NXP Semiconductors · 18 open roles · median 79 d
How we counted: 450 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.