Ph.D. Intern - Analog, Mixed Signal & Circuit Design
$38 - $76 USD yearly
Originally posted 4 September 2026 by the employer.
About the role
This Ph.D. Intern role involves designing, simulating, and verifying analog and mixed-signal circuit blocks.
What you'll do
- Design, simulate, and verify analog and mixed-signal circuit blocks from architecture to silicon bring-up.
- Work on production-grade IP, including high-speed SerDes building blocks, Silicon Photonics driver and receiver circuits, ADC/DAC architectures, PLLs, clock distribution networks, and LDOs in advanced CMOS FinFET processes.
- Use industry-standard tools including Cadence and MATLAB for projects.
- Collaborate with layout engineers to implement and iterate designs.
- Attend and contribute to design reviews.
- Present research framing and design results to engineering teams.
What you'll need
- Currently enrolled in a Ph.D. program in Electrical Engineering or a related field, with a research focus in analog, mixed-signal, or RF circuit design.
- Hands-on experience designing and simulating analog circuit blocks such as PLLs, SerDes building blocks, ADCs, DACs, LDOs, amplifiers, or high-speed I/O.
- Strong fundamentals in transistor-level circuit design, including device physics, noise analysis, linearity, stability, and low-power techniques in advanced CMOS processes.
- Ability to simulate and verify designs independently using industry-standard tools such as Cadence Virtuoso and Spectre.
- Experience with MATLAB or Python for system-level modeling.
- Ability to communicate design decisions and tradeoffs clearly.
Nice to have
- Experience designing in FinFET process nodes (7nm, 5nm, 3nm, or equivalent).
- Familiarity with high-speed serial link architectures, optical transceiver circuits, or Die-to-Die interconnect design.
- Exposure to layout-aware design, parasitic extraction, or post-layout simulation.
- Experience with behavioral modeling in Verilog-A or similar.
Skills: analog circuit design, mixed-signal circuit blocks, PLLs, SerDes building blocks, ADCs
This role has been open 24 days — well below the 93-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
154
|
Median days open
93 d
|
Median salary
$178k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (154 roles · 43 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 154 |
| Open roles in the wider Analog & Mixed-Signal family | 18 | 1393 · 107 employers |
| Median days open | 24 d | 93 d (−69 d vs this employer) |
| Median salary (USD postings) | — | $178k |
Skills observed across this category: analog circuit design, mixed-signal circuit blocks, PLLs, SerDes building blocks, ADCs
Who's hiring in this category
- Analog Devices · 24 open roles · median 76 d
- Infineon Technologies · 14 open roles · median 79 d
- SiTime · 11 open roles · median 188 d
- NVIDIA · 10 open roles · median 56 d
- Qualcomm · 8 open roles · median 56 d
- Broadcom · 7 open roles · median 40 d
How we counted: 154 open Mixed-Signal Design (Mixed Signal) roles from 43 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.