Ph.D. Intern - AI/ML & Design Automation - United States
$37 - $73 USD yearly
Originally posted 10 September 2026 by the employer — open 0 days.
About the role
This Ph.D. Intern role focuses on applying AI/ML techniques to chip design challenges or building and deploying internal AI tools and platforms for engineering workflows.
What you'll do
- Develop and apply ML models to chip design tasks like placement, routing, and timing closure.
- Work with production EDA tool flows and design data from active tapeouts in 3nm and 2nm FinFET and Gate-All-Around processes.
- Build predictive models to reduce design iteration cycles and improve first-pass silicon success rates.
- Design, implement, and evaluate LLM-based tools and agentic workflows for global engineering and operations teams.
- Build retrieval-augmented generation (RAG) pipelines, fine-tuning workflows, and prompt engineering frameworks.
- Evaluate model performance, safety, and reliability in production enterprise environments.
What you'll need
- Currently enrolled in a Ph.D. program in Computer Science, Electrical Engineering, Data Science, or a related field with a research focus in machine learning or AI systems.
- Applied experience training, evaluating, and deploying ML models using frameworks such as PyTorch or TensorFlow.
- Production-quality Python programming, familiarity with Git and software development best practices.
- Rigorous experimental methodology to design experiments, measure results, and draw defensible conclusions from data.
- For hardware track: Coursework or research experience in VLSI design, digital or analog circuit design, computer architecture, or EDA.
- For enterprise track: Design and implement agentic GenAI systems with demonstrated experience across LLMs, multimodal models, RAG pipelines, and agentic protocols such as MCP and A2A.
Nice to have
- Exposure to EDA tools or chip design flows (Cadence, Synopsys, or equivalent).
- Experience with agentic reasoning, planning, and tool-use patterns in multi-agent orchestration frameworks such as n8n or AutoGen.
- Exposure to end-to-end data pipeline development and model deployment.
- Demonstrated ability to independently research and implement concepts from current AI literature and apply them in a working system.
Skills: ML for chip design, EDA automation, design space exploration, LLM-based tools, agentic workflows
This role has been open 0 days — well below the 52-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
43
|
Median days open
52 d
|
Median salary
$193k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (43 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 43 |
| Open roles in the wider Physical Implementation family | 42 | 1423 · 105 employers |
| Median days open | 0 d | 52 d (−52 d vs this employer) |
| Median salary (USD postings) | — | $193k |
Skills observed across this category: ML for chip design, EDA automation, design space exploration, LLM-based tools, agentic workflows
Who's hiring in this category
- NXP Semiconductors · 7 open roles · median 41 d
- Cadence Design Systems · 4 open roles · median 55 d
- NVIDIA · 4 open roles · median 74 d
- Qualcomm · 4 open roles · median 37 d
- Micron Technology · 3 open roles · median 125 d
- Synopsys · 3 open roles · median 22 d
How we counted: 43 open EDA/CAD Engineering (AI EDA Design) roles from 20 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.