Ph.D. Intern - Advanced Packaging & Physical Integration - United States
$37 - $73 USD yearly
Originally posted 10 September 2026 by the employer — open 0 days.
Work on packaging design and analysis for production AI accelerator and connectivity platforms.
About the role
This Ph.D. Intern role focuses on advanced packaging design and physical integration. You will contribute to the integration of compute silicon, high-bandwidth memory, optical I/O, and die-to-die interconnects for custom XPUs, AI accelerators, and high-speed connectivity platforms.
What you'll do
- Perform signal integrity (SI) and power integrity (PI) analysis for high-speed interfaces across multi-die package substrates and interposers.
- Develop and execute thermal and mechanical simulation models for advanced 2.5D and 3D chiplet packages.
- Contribute to physical design and layout of package substrates, RDL interposers, and chiplet integration schemes.
- Collaborate with chip design, assembly, and test engineering teams to validate packaging assumptions.
- Use industry-standard EDA and simulation tools to model and optimize package-level electrical, thermal, and mechanical performance.
- Present analysis results and design recommendations to the engineering team.
What you'll need
- Currently enrolled in a Ph.D. program in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field, with a research focus in advanced packaging, signal/power integrity, thermal engineering, or heterogeneous integration.
- Research or project experience in package-level SI/PI analysis, thermal-mechanical simulation, 2.5D/3D chiplet integration, substrate or interposer design, or high-speed interconnect characterization.
- Strong fundamentals in electromagnetics, heat transfer, or materials mechanics.
- Experience using simulation tools such as Ansys HFSS, Ansys Icepak, Cadence Sigrity, or equivalent.
- Ability to communicate analysis results and design tradeoffs clearly.
Nice to have
- Experience with high-speed serial interface SI analysis, including eye diagram analysis, impedance matching, crosstalk, and return loss, at 100G/lane speeds or above.
- Familiarity with advanced packaging technologies including CoWoS, FOPLP, RDL interposers, or flip-chip BGA.
- Exposure to co-packaged optics (CPO) integration, optical engine assembly, or photonic-electronic co-design.
- Experience with power delivery network (PDN) design and analysis for high-current, high-frequency applications.
- Familiarity with design-for-manufacturing (DFM) and reliability considerations for chiplet-based multi-die packages.
Skills: advanced packaging, chiplet, 2.5D/3D integration, signal integrity, power integrity
This role has been open 0 days — well below the 40-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
69
|
Median days open
40 d
|
Median salary
$206k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (69 roles · 23 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 69 |
| Median days open | 41 d | 40 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Skills observed across this category: advanced packaging, chiplet, 2.5D/3D integration, signal integrity, power integrity
Who's hiring in this category
- Micron Technology · 11 open roles · median 132 d
- Marvell Technology (this employer) · 9 open roles · median 44 d
- AMD · 7 open roles · median 16 d
- Amazon · 5 open roles · median 9 d
- Broadcom · 5 open roles · median 152 d
- NVIDIA · 4 open roles · median 25 d
How we counted: 69 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 23 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.