Performance Modeling Engineer Processor, AI Accelerator, and SoC Architecture- Sr.Staff
$191,800 - $287,800 USD yearly
Originally posted 1 October 2026 by the employer.
About the role
What you'll do
- Develop and maintain transaction-level and analytical performance models for processors, memory hierarchies, interconnects, and accelerators.
- Create detailed models of cache hierarchies, coherent interconnects, memory subsystems, DMA engines, and shared-memory multiprocessor (SMP) systems.
- Evaluate architectural tradeoffs involving performance, power, area, latency, bandwidth, and scalability.
- Analyze workload behavior and identify system bottlenecks through simulation and modeling.
- Perform deep performance analysis of branch prediction, hardware prefetching, speculative execution, load/store architectures, cache coherence protocols, and memory consistency models.
What you'll need
- BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or related field.
- 10 years of industry experience in computer architecture, microarchitecture, or performance modeling.
- Strong understanding of processor architecture and microarchitecture, cache and memory hierarchy design, shared-memory multiprocessor (SMP) systems, and multicore scaling challenges.
- Experience developing Transaction-Level Models (TLM/SystemC), analytical performance models, and architectural simulators.
- Deep knowledge of cache behavior, including capacity and conflict effects, latency analysis, prefetching techniques, memory locality, and coherence interactions.
- Familiarity with modern cache coherence protocols such as ARM CHI, ACE, and MESI/MOESI-based protocols.
- Strong understanding of memory consistency models, atomic operations, synchronization mechanisms, and ordering semantics.
- Strong software development skills in C++, Python, or equivalent languages.
Nice to have
- Experience modeling AI accelerators, CPUs, GPUs, or heterogeneous compute architectures.
- Understanding of Network-on-Chip (NoC) architectures, memory controllers, DDR and HBM memory systems, and virtualization technologies such as SR-IOV.
- Familiarity with formal verification methods for cache coherence and memory ordering.
- Experience correlating pre-silicon performance models with silicon measurements and performance counters.
- Knowledge of power-performance analysis and optimization techniques.
Skills: performance modeling, processor architecture, cache hierarchies, coherent interconnects, memory subsystems
This role has been open 8 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
461
|
Median days open
76 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (461 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 76 | 461 |
| Open roles in the wider Digital Design & Verification family | 389 | 3183 · 114 employers |
| Median days open | 81 d | 76 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: performance modeling, processor architecture, cache hierarchies, coherent interconnects, memory subsystems
Who's hiring in this category
- Qualcomm (this employer) · 77 open roles · median 79 d
- NVIDIA · 60 open roles · median 63 d
- AMD · 36 open roles · median 58 d
- Apple · 32 open roles · median 3 d
- Arm Holdings · 27 open roles · median 106 d
- NXP Semiconductors · 21 open roles · median 108 d
How we counted: 461 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.